LAN91C94 datasheet(21/120 Pages) SMSC

21 / 120 page

The LAN91C94 provides a 16 bit data path into

RAM.

The RAM is private and can only be

accessed by the system via the arbiter.

RAM

memory is managed by the MMU.

Byte and

word accesses to the RAM are supported.

If the system to SRAM bandwidth is insufficient

the

LAN91C94

will

automatically

use

its

IOCHRDY line for flow control.

However, for

ISA buses, IOCHRDY will never be negated.

BUFFER MEMORY

The logical addresses for RAM access are

divided into TX area and RX area. Each one of

the areas is 2 kbytes long and accommodates

one maximum size Ethernet packet.

The TX area is seen by the CPU as a window

through which packets can be loaded into

memory before queuing them in the TX FIFO of

packets.

The TX area can also be used to

examine the transmit completion status after

packet transmission.

The RX area is associated to the output of the

RX FIFO of packets, and is used to access

receive packet data and status information.

The logical address is specified by loading the

address pointer register.

The pointer can

automatically increment on accesses.

All accesses to the RAM are done via I/O space.

A bit in the address pointer also specifies if the

address refers to the TX or RX area.

In the TX area, the host CPU has access to the

transmit

packet

being

prepared

for

transmission. In the RX area, it has access to

the first receive packet not processed by the

CPU yet.

The FIFO of packets, existing beneath the TX

and RX areas, is managed by the MMU. The

MMU

dynamically

allocates

and

releases

memory to be used by the transmit and receive

functions.

The MMU related parameters for the LAN91C94

are:

RAM size

4608 bytes (internal)

Max. number of packets

Max. pages per packet

Page size

256 bytes

LAN91C94 Datasheet(PDF) 21 Page - SMSC Corporation

LAN91C94 Datasheet(HTML) 21 Page - SMSC Corporation

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