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LAN91C94 Datasheet(PDF) 100 Page - SMSC Corporation |
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LAN91C94 Datasheet(HTML) 100 Page - SMSC Corporation |
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100 / 120 page ![]() 100 FIGURE 25 - ISA CONSECUTIVE READ AND WRITE CYCLES t20 A0-15 AEN, nSBHE nIOCS16 nIOWR D0-D15 VALID ADDRESS VALID ADDRESS nIORD t 9 t 10 Z Z Z VALI D DATA VALI D DATA IOCHRDY Z Z Control Act ive to IOCHRDY Low IOCHRDY Low Pulse Width* Cycle ti me** Paramete r min typ max units 100 185 15 150 ns ns ns t 9 t10 t20 * Note: Assuming NO WAI T ST = 0 i n configuration register and cycle time observed. **Note: The cycle time is defined onl y for accesses to the Data Register as foll ows: For Data Register Read - From nIORD falling to next nIO RD falli ng For Data Register Write - From nIOWR risi ng to next nIOWR risi ng |
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