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LAN91C94 Datasheet(PDF) 58 Page - SMSC Corporation |
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LAN91C94 Datasheet(HTML) 58 Page - SMSC Corporation |
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58 / 120 page  58 I/O SPACE - BANK2 OFFSET C NAME INTERRUPT STATUS REGISTER TYPE READ ONLY SYMBOL IST ERCV INT EPH INT RX_OVRN INT ALLOC INT TX EMPTY INT TX INT RCV INT X 0 0 0 0 1 0 0 OFFSET C NAME INTERRUPT ACKNOWLEDGE REGISTER TYPE WRITE ONLY SYMBOL ACK ERCV INT RX_OVRN INT TX EMPTY INT TX INT OFFSET D NAME INTERRUPT MASK REGISTER TYPE READ/WRITE SYMBOL MSK ERCV INT EPH INT RX_OVRN INT ALLOC INT TX EMPTY INT TX INT RCV INT X 0 0 0 0 0 0 0 This register can be read and written as a word or as two individual bytes. The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. An enabled bit being set will cause a hardware interrupt. EPH INT - Set when the Ethernet Protocol Handler section indicates one out of various possible special conditions. This bit merges exception type of interrupt sources, whose service time is not critical to the execution speed of the low level drivers. The exact nature of the interrupt can be obtained from the EPH |
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