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LAN91C94 Datasheet(PDF) 46 Page - SMSC Corporation |
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LAN91C94 Datasheet(HTML) 46 Page - SMSC Corporation |
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46 / 120 page ![]() 46 I/O SPACE - BANK1 OFFSET 2 NAME BASE ADDRESS REGISTER TYPE READ/WRITE SYMBOL BAR In ISA mode, this register holds the address decode options chosen for the I/O and ROM spaces. It is part of the EEPROM saved setup and is not usually modified during run-time. HIGH BYTE A15 A14 A13 A9 A8 A7 A6 A5 0 0 0 1 1 0 0 0 LOW BYTE ROM SIZE RA18 RA17 RA16 RA15 RA14 0 1 1 0 0 1 1 X A15 - A13 and A9 - A5 - These bits are compared in ISA mode against the I/O address on the bus to determine the IOBASE for LAN91C94 registers. The 64k I/O space is fully decoded by the LAN91C94 down to a 16 location space, therefore the unspecified address lines A4, A10, A11 and A12 must be all zeros. ROM SIZE - Determines the ROM decode area in ISA mode memory space as follows: 00 = ROM disable 01 = 16k: RA14-18 define ROM select. 10 = 32k: RA15-18 define ROM select. 11 = 64k: RA16-18 define ROM select. RA18-RA14 - These bits are compared against the memory address on the bus to determine if the ROM is being accessed, as a function of the ROM SIZE. ROM accesses are read only memory accesses defined by nMEMRD going low. For a full decode of the address space unspecified upper address lines have to be: A19 = "1" , A20-A23 lines are not directly decoded, however ISA systems will only activate nSMEMRD only when A20-A23=0. All bits in this register are loaded from the serial EEPROM. The I/O base decode defaults to 300h (namely, the high byte defaults to 18h). ROM SIZE defaults to 01. ROM decode defaults to CC000 (namely the low byte defaults to 67h). As an example: |
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