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AT83C5111 Datasheet(PDF) 33 Page - ATMEL Corporation |
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AT83C5111 Datasheet(HTML) 33 Page - ATMEL Corporation |
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33 / 86 page  33 AT8xC5111 4190A–8051–11/02 Table 8. BDRCON Register BDRCON - Baud Rate Control Register (9Bh) Reset value = XXX0 0000b 7654 3210 - - - BRR TBCK RBCK SPD SRC Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4BRR Baud Rate Run Control bit Clear to stop the internal Baud Rate Generator. Set to start the internal Baud Rate Generator. 3TBCK Transmission Baud rate Generator Selection bit for UART Clear to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator. 2RBCK Reception Baud Rate Generator Selection bit for UART Clear to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator. 1SPD Baud Rate Speed Control bit for UART Clear to select the SLOW Baud Rate Generator. Set to select the FAST Baud Rate Generator. 0SRC Baud Rate Source Select bit in Mode 0 for UART Clear to select FOSC/12 as the Baud Rate Generator (FOSC/6 in X2 mode). Set to select the internal Baud Rate Generator for UARTs in mode 0. |
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