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BLUENRG-2 Datasheet(PDF) 135 Page - STMicroelectronics |
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BLUENRG-2 Datasheet(HTML) 135 Page - STMicroelectronics |
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135 / 190 page ![]() BlueNRG-2 Functional details DocID030675 Rev 2 135/190 Bit Field name Reset RW Description 6 TNCIEN 0x0 RW Timer interrupt C enable: 0: Interrupt disabled. 1: Interrupt enabled 7 TNDIEN 0x0 RW Timer interrupt D enable: 0: Interrupt disabled. 1: Interrupt enabled. 31:8 RESERVED 0x0 R RESERVED Table 168: MFTX - TNICLR register description: address offset MFTX_BASE_ADDR+0x20 Bit Field name Reset RW Description 0 TNACLR 0x0 W 1: clear the timer pending flag A 1 TNBCLR 0x0 W 1: clear the timer pending flag B. 2 TNCCLR 0x0 W 1: clear the timer pending flag C. 3 TNDCLR 0x0 W 1: clear the timer pending flag D. 31:4 RESERVED 0x0 R RESERVED 3.14 Watchdog 3.14.1 Introduction The watchdog timer provides a way of recovering from software crashes. The watchdog monitors the interrupt and asserts a Reset signal if the interrupt remains unserved for the entire programmed period. The watchdog clock is used to generate a regular interrupt, depending on a programmed value. It is counting down at a fixed frequency around 32.768 kHz provided either by embedded RCO or by the external XO 32 kHz. Main features are: 32-bit down counter at fixed frequency 32.768 kHz Generate an interrupt each time the counter reaches zero Generate an internal reset that reboot the system if the generated interrupt is not cleared by software and a second interrupt occurs 3.14.2 Functional description The watchdog timer is a 32-bit down counter that divides the clock input to produce an interrupt. The divide ratio is fully programmable and controls the interrupt interval, which can be calculated as: Interrupt interval = (WDT_LOAD + 1) / (clock frequency in Hz). The table below shows examples of WDT_LOAD values. Table 169: Watchdog interrupt interval WDT_LOAD Interrupt interval (ms) 4294967295 131072000 65535 2000 |
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