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BLUENRG-2 Datasheet(PDF) 133 Page - STMicroelectronics |
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BLUENRG-2 Datasheet(HTML) 133 Page - STMicroelectronics |
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133 / 190 page  BlueNRG-2 Functional details DocID030675 Rev 2 133/190 Bit Field name Reset RW Description 31:16 RESERVED 0x0 R RESERVED Table 163: MFTX – TNCNT2 register description: address offset MFTX_BASE_ADDR+0x0C Bit Field name Reset RW Description 31:0 TNCNT2 0x0000 RW Register counter of timer2. 31:16 RESERVED 0x0 R RESERVED Table 164: MFTX – TNPRSC register description: address offset MFTX_BASE_ADDR+0x10 Bit Field name Reset RW Description 7:0 TNPRSC 0x00 RW Clock prescaler register. 31:8 RESERVED 0x0 R RESERVED Table 165: MFTX - TNCKC register description: address offset MFTX_BASE_ADDR+0x14 Bit Field name Reset RW Description 2:0 TNC1CSEL 0x0 RW Define the clock mode for timer/counter 1: 000b: No clock (timer/counter 1 stopped). 001b: Prescaled system clock. 010b: External event on TnB (mode 1 and 3 only). 011b: Pulse accumulate (mode 1 and 3 only). 100b: Low-speed clock. 5:3 TNC2CSEL 0x0 RW Define the clock mode for timer/counter 2: 000b: No clock (timer/counter 2 stopped). 001b: Prescaled system clock. 010b: External event on TnB (mode 1 and 3 only). 011b: Pulse accumulate (mode 1 and 3 only). 100b: Low-speed clock. 31:6 RESERVED 0x0 R RESERVED Table 166: MFTX - TNMCTRL register description: address offset MFTX_BASE_ADDR+0x18 Bit Field name Reset RW Description 1:0 TNMDSEL 0x0 RW MFTX mode select: 00b: Mode 1 or 1a: PWM mode and system timer or pulse train 01b: Mode 2: Dual-input capture and system timer 10b: Mode 3: Dual independent timer/counter 11b: Mode 4: Single timer and single input capture 2 TNAEDG 0x0 RW TnA edge polarity: 0: Input is sensitive to falling edges. 1: Input is sensitive to rising edges. 3 TNBEDG 0x0 RW TnB edge polarity: 0: Input is sensitive to falling edges. 1: Input is sensitive to rising edges. |
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