CS5530A datasheet(107/259 Pages) NSC

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Functional Description (Continued)

3.5.7

External Real-Time Clock Interface

I/O Ports 070h and 071h decodes are provided to interface

to an external real-time clock controller. I/O Port 070h, a

write only port, is used to set up the address of the desired

data in the controller. This causes the address to be placed

on the ISA data bus, and the RTCALE signal to be trig-

gered. A read of I/O Port 071h causes an ISA I/O read

cycletobeperformed while asserting the RTCCS#signal.

A write to I/O Port 071h causes an ISA I/O write cycle to be

performed with the desired data being placed on the ISA

busand theRTCCS#signal tobeasserted. RTCCS#/

SMEMW# and RTCALE/SMEMR# are multiplexed pins.

The function selection is made through F0 Index 53h[2].

The connection between the CS5530A and an external

real-time clock is shown in Figure 3-18.

The CS5530A also provides the RTC Index Shadow Regis-

ter (F0 Index BBh) to store the last write to I/O Port 070h.

Table3-53shows thebit formatsfor the associatedregis-

ters for interfacing with an external real-time clock.

Figure 3-18. External RTC Interface

SD[7:0]

RTCALE/SMEMR#

IOR#

IOW#

RTC

RTCCS#/SMEMW#

IRQ8#

Table 3-53. Real-Time Clock Registers

Bit

Description

I/O Port 070h (WO)

RTC Address Register

NMI Mask: 0 = Enable; 1 = Mask.

6:0

RTC Register Index: A write of this register sends the data out on the ISA bus and also causes RTCALE to be triggered.

Note: This register is shadowed within the CS5530A and is read through the RTC Shadow Register (F0 Index BBh).

I/O Port 071h (R/W)

RTC Data Register

A read of this register returns the value of the register indexed by the RTC Address Register plus initiates a RTCCS#.

A write of this register sets the value into the register indexed by the RTC Address Register plus initiates a RTCCS#.

F0 Index BBh

RTC Index Shadow Register (RO)

Reset Value = xxh

7:0

RTC Index Shadow (Read Only): The RTC Shadow register contains the last written value of the RTC Index

F0 Index 53h

Alternate CPU Support Register (R/W)

Reset Value = 00h

RTC Enable/RTC Pin Configuration: 0 = SMEMW# (Pin AF3) and SMEMR# (Pin AD4), RTC decode disabled;

1 = RTCCS# (Pin AF3) and RTCALE (Pin AD4), RTC decode enabled.

Note: The RTC Index Shadow Register (F0 Index BBh) is independent of the setting of this bit.

CS5530A Datasheet(PDF) 107 Page - National Semiconductor (TI)

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