CS5530A datasheet(153/259 Pages) NSC

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4.3

CHIPSET REGISTER SPACE

The Chipset Register Space of the CS5530A is comprised

of five separate functions (Function 0 through 4, F0-F4),

each with its own register space and PCI header registers.

F1-F4 have memory or I/O mapped registers from a Base

Address Register (BAR). The PCI header registers in all

functions are very similar.

F0: Bridge Configuration Register Space

F1: SMI Status and ACPI Timer Register Space

F2: IDE Controller Register Space

F3: XpressAUDIO Subsystem Register Space

F4: Video Controller Register Space

4.3.1

Bridge Configuration Registers - Function 0

The register space designated as Function 0 (F0) contains

registers used to configure features (e.g., power manage-

ment) and functionality unique to the CS5530A. All regis-

ters in Function 0 are directly accessed (i.e., there are no

memory or I/O mapped registers in F0). Table 4-15 gives

the bit formats for these registers.

The registers at F0 Index 50h-FFh can also be accessed at

F1BAR+Memory Offset 50h-FFh. The preferred method is

to program these registers through the F0 register space.

If theF0PCI ConfigurationTrapbit (F0Index 41h[0]) is

enabled and an access is attempted to any of the F0 PCI

header and bridge configuration registers except F0 Index

40h-43h, an SMI is generated instead.

Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers

Bit

Description

Index 00h-01h

Vendor Identification Register (RO)

Reset Value = 1078h

15:0

Vendor Identification Register (Read Only)

Index 02h-03h

Device Identification Register (RO)

Reset Value = 0100h

15:0

Device Identification Register (Read Only)

Index 04h-05h

PCI Command Register (R/W)

Reset Value = 000Fh

15:10

Reserved: Set to 0.

Fast Back-to-Back Enable (Read Only): This function is not supported when the CS5530A is a master. It is always

disabled (always reads 0).

SERR#: Allow SERR# assertion on detection of special errors. 0 = Disable (Default);1 =Enable.

Wait Cycle Control (Read Only): This function is not supported in the CS5530A. It is always disabled

(always reads 0).

Parity Error: Allow the CS5530A to check for parity errors on PCI cycles for which it is a target, and to assert PERR# when

a parity error is detected. 0 = Disable (Default); 1 = Enable.

VGA Palette Snoop Enable (Read Only): This function is not supported in the CS5530A. It is always disabled (always

reads 0).

Memory Write and Invalidate: Allow the CS5530A to do memory write and invalidate cycles, if the PCI Cache Line Size

Special Cycles: Allow the CS5530A to respond to special cycles. 0 = Disable; 1 = Enable (Default).

This bit must be enabled to allow the CPU Warm Reset internal signal to be triggered from a CPU Shutdown cycle.

Bus Master: Allow the CS5530A bus mastering capabilities. 0 = Disable; 1 = Enable (Default).

This bit must be set to 1.

Memory Space: Allow the CS5530A to respond to memory cycles from the PCI bus. 0 = Disable; 1 = Enable (Default).

I/O Space: Allow the CS5530A to respond to I/O cycles from the PCI bus. 0 = Disable; 1 = Enable (Default).

CS5530A Datasheet(PDF) 153 Page - National Semiconductor (TI)

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