CS5530A datasheet(155/259 Pages) NSC

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Index 40h

PCI Function Control Register 1 (R/W)

Reset Value = 89h

PCI Interrupt Acknowledge Cycle Response: Allow the CS5530A responds to PCI interrupt acknowledge cycles.

0 = Disable; 1 = Enable.

Single Write Mode: The CS5530A accepts only single cycle write transfers as a slave on the PCI bus and performs a target

disconnect with the first data transferred. 0 = Disable (accepts burst write cycles); 1 = Enable.

Single Read Mode: The CS5530A accepts only single cycle read transfers as a slave on the PCI bus and performs a target

disconnect with the first data transferred. 0 = Disable (accepts burst read cycles); 1 = Enable.

Retry PCI Cycles: Retry inbound PCI cycles if data is buffered and waiting to go outbound on PCI. 0 = No Retry; 1 = Retry.

Write Buffer: PCI slave write buffer. 0 = Disable; 1 = Enable.

2:1

Reserved: Set to 0.

BS8/16: This bit can not be written. Always = 1.

Note: Bits 6 and 5 emulate the behavior of first generation SIO devices developed for PCI. They should normally remain cleared.

Index 41h

PCI Function Control Register 2 (R/W)

Reset Value = 10h

Burst to Beat: If this bit is set to 1, the CS5530A performs a single access from the PCI bus. If set to 0, burst accesses are

enabled.

F2 IDE Configuration Trap: 0 = Disable; 1 = Enable.

If this bit is enabled and an access is attempted to one of the F2 PCI header registers, an SMI is generated instead.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9].

Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5].

PERR# Signals SERR#: Assert SERR# any time that PERR# is asserted or detected active by the CS5530A (allows

PERR# assertion to be cascaded to NMI (SMI) generation in the system). 0 = Disable; 1 = Enable.

Write Buffer Enable: Allow 16-byte buffering for X-Bus to PCI bus writes. 0 = Disable; 1 = Enable.

F1 Power Management Configuration Trap: 0 = Disable; 1 = Enable.

If this bit is enabled and an access occurs to one of the F1 PCI configuration header registers, an SMI is generated.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9].

Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5].

2:1

Subtractive Decode: These bits determine the point at which the CS5530A accepts cycles that are not claimed by another

device. The CS5530A defaults to taking subtractive decode cycles in the default cycle clock, but can be moved up to the

Slow Decode cycle point if all other PCI devices decode in the fast or medium clocks. Disabling subtractive decode must be

done with care, as all ISA and ROM cycles are decoded subtractively.

00 = Default sample (4th clock from FRAME# active)

01 = Slow sample (3rd clock from FRAME# active)

1x = No subtractive decode

F0 PCI Configuration Trap: 0 = Disable; 1 = Enable.

If this bit is enabled and an access is attempted to any of the F0 PCI header registers except F0 Index 40h-43h, an SMI is

generated instead.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9].

Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5].

Index 42h

PCI Function Control Register 3 (R/W)

Reset Value = ACh

USB SMI I/O Configuration: Route USB-generated SMI to SMI# pin. 0 = Disable;

1 = Enable, USB-generated SMI pulls SMI# pin active (low).

USB SMI Power Mgmnt Configuration: Route USB-generated SMI to Top Level SMI Status Register, F1BAR+Memory

Offset 00h/02h[14]. 0 = Disable; 1 = Enable.

Delayed Transactions: Allow delayed transactions on the PCI bus. 0 = Disable; 1 = Enable.

Also see F0 Index 43h[1].

DMA Priority: Allow USB DMA to have priority over other DMA requests. 0 = Disable; 1 = Enable.

No X-Bus ARB, Buffer Enable: When the CS5530A is a PCI target, allow buffering of PCI transactions without X-Bus

arbitration. 0 = Disable; 1 = Enable.

HOLD_REQ# (Pin H26): HOLD_REQ# signal (pin H26). 0 = Disable; 1 = Enable.

Note: Although the HOLD_REQ# signal function is no longer applicable, this bit must remain at its reset value (i.e.,

enabled, set to 1) for non-preemptive arbitration to operate correctly.

Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

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