CS5530A datasheet(159/259 Pages) NSC

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Index 5Ch

PCI Interrupt Steering Register 1 (R/W)

Reset Value = 00h

7:4

INTB# Target Interrupt: Selects target interrupt for INTB#.

0000 = Disable

0100 = IRQ4

1000 = RSVD

1100 = IRQ12

0001 = IRQ1

0101 = IRQ5

1001 = IRQ9

1101 = RSVD

0010 = RSVD

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

0011 = IRQ3

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

3:0

INTA# Target Interrupt: Selects target interrupt for INTA#.

0000 = Disable

0100 = IRQ4

1000 = RSVD

‘

1100 = IRQ12

0001 = IRQ1

0101 = IRQ5

1001 = IRQ9

1101 = RSVD

0010 = RSVD

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

0011 = IRQ3

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt

compatibility.

Index 5Dh

PCI Interrupt Steering Register 2 (R/W)

Reset Value = 00h

7:4

INTD# Target Interrupt: Selects target interrupt for INTD#.

0000 = Disable

0100 = IRQ4

1000 = RSVD

1100 = IRQ12

0001 = IRQ1

0101 = IRQ5

1001 = IRQ9

1101 = RSVD

0010 = RSVD

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

0011 = IRQ3

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

3:0

INTC# Target Interrupt: Selects target interrupt for INTC#.

0000 = Disable

0100 = IRQ4

1000 = RSVD

1100 = IRQ12

0001 = IRQ1

0101 = IRQ5

1001 = IRQ9

1101 = RSVD

0010 = RSVD

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

0011 = IRQ3

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt

compatibility.

Index 5Eh-6Fh

Reserved

Reset Value = xxh

Index 70h-71h

General Purpose Chip Select Base Address Register (R/W)

Reset Value = 0000h

15:0

General Purpose Chip Select I/O Base Address: This 16-bit value represents the I/O base address used to enable the

assertion of the GPCS# signal.

This register, together with General Purpose Chip Select Control Register (F0 Index 72h) is used to configure the

operation of the GPCS# pin.

Index 72h

General Purpose Chip Select Control Register (R/W)

Reset Value = 00h

General Purpose Chip Select: GPCS# (pin AF26). 0 = Disable; 1 = Enable.

If the GPCS# signal is disabled (i.e., this bit = 0) its output is permanently driven high.

Writes Result in Chip Select: Writes to configured I/O address (base address configured in F0 Index 70h and range con-

figured in bits [4:0]) causes GPCS# signal to be asserted. 0 = Disable; 1 = Enable.

Reads Result in Chip Select: Reads from configured I/O address (base address configured in F0 Index 70h and range

configured in bits [4:0]) causes GPCS# signal to be asserted. 0 = Disable; 1 = Enable.

4:0

General Purpose Chip Select I/O Address Range: This 5-bit field selects the range of GPCS# signal.

00000 = 1 byte

01111 = 16 bytes

00001 = 2 bytes

11111 = 32 bytes

00011 = 4 bytes

All other combinations are reserved.

00111 = 8 bytes

Note: This register, together with General Purpose Chip Select Base Address Register (F0 Index 70h) is used to configure the opera-

tion of the GPCS# pin.

Index 73h-7Fh

Reserved

Reset Value = xxh

Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

CS5530A Datasheet(PDF) 159 Page - National Semiconductor (TI)

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