CS5530A datasheet(158/259 Pages) NSC

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Revision 1.1

Game Port Write SMI: Allow SMI generation on writes to game port (I/O Port 200h and 201h). 0 = Disable; 1 = Enable.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 84h/F4h[4].

For “Game Port Read SMI”, see F0 Index 83h[4].

RTC Enable/RTC Pin Configuration: 0 = SMEMW# (Pin AF3) and SMEMR# (Pin AD4), RTC decode disabled;

1 = RTCCS# (Pin AF3) and RTCALE (Pin AD4), RTC decode enabled.

Note: The RTC Index Shadow Register (F0 Index BBh) is independent of the setting of this bit.

Reserved: Set to 1 after register reset. Failure to do this leaves IRQ13 in an unsupported mode.

Generate SMI on A20M# toggle: 0 = Disable; 1 = Enable. This bit must be set to 1.

SMI status is reported in F1BAR+Memory Offset 00h/02h[7] (only).

Index 54h-59h

Reserved

Reset Value = xxh

Index 5Ah

Decode Control Register 1 (R/W)

Reset Value = 03h

Secondary Floppy Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port

372h, 373h, 375h, and 377h. 0 = Subtractive; 1 = Positive.

Primary Floppy Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port

3F2h, 3F4h, 3F5h, and 3F7h. 0 = Subtractive; 1 = Positive.

COM4 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 2E8h-2EFh.

0 = Subtractive; 1 = Positive.

COM3 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 3E8h-3EFh.

0 = Subtractive; 1 = Positive.

COM2 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 2F8h-2FFh.

0 = Subtractive; 1 = Positive.

COM1 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 3F8h-3FFh.

0 = Subtractive; 1 = Positive.

Keyboard Controller Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port

060h and 064h (and 062h/066h if enabled). 0 = Subtractive; 1 = Positive.

Real Time Clock Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port

070h-7Fh. 0 = Subtractive; 1 = Positive.

Note: Positive decoding by the CS5530A speeds up the I/O cycle time. These I/O Ports do not exist in the CS5530A. It is assumed that

if positive decode is enabled, the port exists on the ISA bus.

Index 5Bh

Decode Control Register 2 (R/W)

Reset Value = 20h

Keyboard I/O Port 062h/066h Decode: This alternate port to the keyboard controller is provided in support of the 8051SL

notebook keyboard controller mailbox. 0 = Disable; 1 = Enable.

Reserved: Set to 0.

BIOS ROM Positive Decode: Selects PCI positive or subtractive decoding for accesses to the configured ROM space.

0 = Subtractive; 1 = Positive.

ROM configuration is at F0 Index 52h[2:0].

Secondary IDE Controller Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 170h-

177h and 376h. 0 = Subtractive; 1 = Positive.

Note: Subtractive Decode mode disables this IDE controller entirely and routes any register references to the ISA bus.

Primary IDE Controller Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 1F0h-1F7h

and 3F6h. 0 = Subtractive; 1 = Positive.

Note: Subtractive Decode mode disables this IDE controller entirely and routes any register references to the ISA bus.

LPT3 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 278h-27Fh.

0 = Subtractive; 1 = Positive.

This bit does not affect 7BCh-7BEh, which is always decoded subtractively.

LPT2 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 378h-37Fh.

0 = Subtractive; 1 = Positive.

This bit does not affect 678h-67Ah, which is always decoded subtractively.

LPT1 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 3BCh-3BFh.

0 = Subtractive; 1 = Positive.

This bit does not affect 778h-77Ah, which is always decoded subtractively.

Note: Positive decoding by the CS5530A speeds up the I/O cycle time. The keyboard, LPT3, LPT2, and LPT1 I/O Ports do not exist in

the CS5530A. It is assumed that if positive decode is enabled, the port exists on the ISA bus.

Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

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