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MMPF0200 Datasheet(PDF) 18 Page - NXP Semiconductors |
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MMPF0200 Datasheet(HTML) 18 Page - NXP Semiconductors |
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18 / 114 page  18 NXP Semiconductors PF0200 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Figure 6. Default start-up sequence PU CONFIG, SEQ_CLK_SPEED 1.0 ms 2.0 ms 1.0 ms 1.0 ms 0.5 ms PU CONFIG, SWDVS_CLK 6.25 mV/ μs 1.5625 mV/ μs 12.5 mV/ μs 12.5 mV/ μs6.25 mV/μs PU CONFIG, PWRON Level sensitive SW1AB CONFIG SW1AB Single Phase, 2.0 MHz SW2 CONFIG 2.0 MHz SW3A CONFIG SW3AB Single Phase, 2.0 MHz SW3B CONFIG 2.0 MHz PG EN RESETBMCU in Default Mode Table 8. Start-up configuration (continued) Registers Default configuration Pre-programmed OTP configuration All devices F0 F3 F4 F6 UVDET LICELL VIN VSNVS PWRON SW1A/B SW2 VGEN2 SW3A/B VREFDDR VGEN4 VGEN5 VGEN6 RESETBMCU tD1 tD3 tD4 tD4 tR1 tR3 tR3 tR3 tD5 tR4 tR2 tD2 1V *VSNVS will start from 1.0 V if LICELL is valid before VIN. |
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