MMPF0200 datasheet(33/114 Pages) NXP

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NXP Semiconductors

PF0200

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

When in Standby mode, the regulator outputs the voltage programmed in its standby voltage register and will operate in the mode selected

by the SWxMODE[3:0] bits. Upon exiting Standby mode, the regulator will return to its normal switching mode and its output voltage

programmed in its voltage register.

Any regulators whose SWxOMODE bit is set to “1” will enter Sleep mode if a PWRON turn-off event occurs, and any regulator whose

SWxOMODE bit is set to “0” will be turned off. In Sleep mode, the regulator outputs the voltage programmed in its off (Sleep) voltage

register and operates in the PFM mode. The regulator will exit the Sleep mode when a turn-on event occurs. Any regulator whose

SWxOMODE bit is set to “1” will remain on and change to its normal configuration settings when exiting the Sleep state to the ON state.

Any regulator whose SWxOMODE bit is set to “0” will be powered up with the same delay in the start-up sequence as when powering On

from Off. At this point, the regulator returns to its default ON state output voltage and switch mode settings.

Table 23 shows the control bits in Sleep mode. When Sleep mode is activated by the SWxOMODE bit, the regulator will use the set point

as programmed by SW1ABOFF[5:0] for SW1A/B and by SWxOFF[6:0] for SW2 and SW3A/B.

Dynamic voltage scaling

To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor.

1. Normal operation: The output voltage is selected by I2C bits SW1AB[5:0] for SW1A/B and SWx[6:0] for SW2 and SW3A/B. A

voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 32 and Table 33.

2. Standby Mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the lowest state

retention voltage of a given processor; it is selected by I2C bits SW1ABSTBY[5:0] for SW1A/B and by bits SWxSTBY[6:0] for SW2

and SW3A/B. Voltage transitions initiated by a Standby event are governed by the SW1ABDVSSPEED[1:0] and

SWxDVSSPEED[1:0] I2C bits shown in Table 32 and Table 33, respectively.

3. Sleep Mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest state

retention voltage of a given processor; it is selected by I2C bits SW1ABOFF[5:0] for SW1A/B and by bits SWxOFF[6:0] for SW2,

and SW3A/B. Voltage transitions initiated by a turn-off event are governed by the SW1ABDVSSPEED[1:0] and

SWxDVSSPEED[1:0] I2C bits shown in Table 32 and Table 33, respectively.

Table 30, Table 31, Table 32, and Table 33 summarize the set point control and DVS time stepping applied to all regulators.

Table 30. DVS control logic for SW1A/B

STANDBY

Set Point Selected by

SW1AB[5:0]

SW1ABSTBY[5:0]

Table 31. DVS control logic for SW2 and SW3A/B

STANDBY

Set Point Selected by

SWx[6:0]

SWxSTBY[6:0]

Table 32. DVS speed selection for SW1A/B

SW1ABDVSSPEED[1:0]

Function

25 mV step each 2.0

μs

01 (default)

25 mV step each 4.0

μs

25 mV step each 8.0

μs

25 mV step each 16

μs

MMPF0200 Datasheet(PDF) 33 Page - NXP Semiconductors

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