MMPF0200 datasheet(59/114 Pages) NXP

59 / 114 page

NXP Semiconductors

PF0200

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Figure 18. Boost regulator architecture

6.4.5.1

SWBST setup and control

Boost regulator control is done through a single register SWBSTCTL described in Table 72. SWBST is included in the power-up sequence

if its OTP power-up timing bits, SWBST_SEQ[4:0], are not all zeros.

Table 72. Register SWBSTCTL - ADDR 0x66

Name

Bit #

R/W

Default

Description

SWBST1VOLT

1:0

R/W

0x00

Set the output voltage for SWBST

00 = 5.000 V

01 = 5.050 V

10 = 5.100 V

11 = 5.150 V

SWBST1MODE

3:2

0x02

Set the Switching mode on Normal operation

00 = OFF

01 = PFM

10 = Auto (Default)(52)

11 = APS

UNUSED

–

0x00

UNUSED

SWBST1STBYMODE

6:5

R/W

0x02

Set the Switching mode on Standby

00 = OFF

01 = PFM

10 = Auto (Default)(52)

11 = APS

UNUSED

–

0x00

UNUSED

Notes

52.

In Auto mode, the controller automatically switches between PFM and APS modes depending on the load current.

The SWBST regulator starts up by default in the Auto mode, if SWBST is part of the startup sequence.

SWBSTLX

VOBST

Driver

Controller

Internal

Compensation

I2C

Interface

SWBSTMODE

VREFUV

VREF

VIN

LBST

CINBST

DBST

SWBSTFB

RSENSE

VREFSC

SWBSTFAULT

COSWBST

SWBSTIN

MMPF0200 Datasheet(PDF) 59 Page - NXP Semiconductors

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