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MMPF0200 Datasheet(PDF) 93 Page - NXP Semiconductors |
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MMPF0200 Datasheet(HTML) 93 Page - NXP Semiconductors |
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93 / 114 page ![]() NXP Semiconductors 93 PF0200 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 121. Extended page 1 Address Register Name TYPE Default BITS[7:0] 7 6 5 4 3 2 1 0 80 OTP FUSE READ EN R/W 8'b000x_xxx0 –– – – – – – OTP FUSE READ EN 00 0 x x x x0 84 OTP LOAD MASK R/W 8'b0000_0000 START RL PWBRTN FORCE PWRCTL RL PWRCTL RL OTP RL OTP ECC RL OTP FUSE RL TRIM FUSE 00 0 0 0 0 0 0 8A OTP ECC SE1 R 8'bxxx0_0000 – – – ECC5_SE ECC4_SE ECC3_SE ECC2_SE ECC1_SE xx x 0 0 0 0 0 8B OTP ECC SE2 R 8'bxxx0_0000 – – – ECC10_SE ECC9_SE ECC8_SE ECC7_SE ECC6_SE xx x 0 0 0 0 0 8C OTP ECC DE1 R 8'bxxx0_0000 – – – ECC5_DE ECC4_DE ECC3_DE ECC2_DE ECC1_DE xx x 0 0 0 0 0 8D OTP ECC DE2 R 8'bxxx0_0000 – – – ECC10_DE ECC9_DE ECC8_DE ECC7_DE ECC6_DE xx x 0 0 0 0 0 A0 OTP SW1AB VOLT R/W 8'b00xx_xxxx –– SW1AB_VOLT[5:0] 00 x x x x x x A1 OTP SW1AB SEQ R/W 8'b000x_xxXx – SW1AB_SEQ[4:0] 00 0 x x x X x A2 OTP SW1AB CONFIG R/W 8'b0000_xxxx –– – – SW1_CONFIG[1:0] SW1AB_FREQ[1:0] 00 0 0 x x x x AC OTP SW2 VOLT R/W 8'b0xxx_xxxx – SW2_VOLT[5:0] 0x x x x x xx AD OTP SW2 SEQ R/W 8'b000x_xxxx –– SW2_SEQ[4:0] 00 0 x x x x x AE OTP SW2 CONFIG R/W 8'b0000_00xx –– – – – – SW2_FREQ[1:0] 00 0 0 0 0 x x B0 OTP SW3A VOLT R/W 8'b0xxx_xxxx – SW3A_VOLT[6:0] 0x x x x x xx B1 OTP SW3A SEQ R/W 8'b000x_xxxx –– SW3A_SEQ[4:0] 00 0 x x x x x B2 OTP SW3A CONFIG R/W 8'b0000_xxxx –– – – SW3_CONFIG[1:0] SW3A_FREQ[1:0] 00 0 0 x x x x |
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