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MMPF0200 Datasheet(PDF) 83 Page - NXP Semiconductors |
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MMPF0200 Datasheet(HTML) 83 Page - NXP Semiconductors |
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83 / 114 page  NXP Semiconductors 83 PF0200 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS 6.5.3 Interrupt handling The system is informed about important events based on interrupts. Unmasked interrupt events are signaled to the processor by driving the INTB pin low. Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each interrupt can be cleared by writing a “1” to the appropriate bit in the Interrupt Status register; this will also cause the INTB pin to go high. If there are multiple interrupt bits set the INTB pin will remain low until all are either masked or cleared. If a new interrupt occurs while the processor clears an existing interrupt bit, the INTB pin will remain low. Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high, the INTB pin will not go low. A masked interrupt can still be read from the Interrupt Status register. This gives the processor the option of polling for status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the device to determine if any interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked interrupt bit was already high, the INTB pin will go low after unmasking. The sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources. They are read only, and not latched or clearable. Interrupts generated by external events are debounced; therefore, the event needs to be stable throughout the debounce period before an interrupt is generated. Nominal debounce periods for each event are documented in the INT summary Table 100 . Due to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly. 6.5.4 Interrupt bit summary Table 100 summarizes all interrupt, mask, and sense bits associated with INTB control. For more detailed behavioral descriptions, refer to the related chapters. Table 100. Interrupt, mask and sense bits Interrupt Mask Sense Purpose Trigger Debounce time (ms) LOWVINI LOWVINM LOWVINS Low Input Voltage Detect Sense is 1 if below 2.80 V threshold H to L 3.9(74) PWRONI PWRONM PWRONS Power on button event H to L 31.25(74) Sense is 1 if PWRON is high. L to H 31.25 THERM110 THERM110M THERM110S Thermal 110 °C threshold Sense is 1 if above threshold Dual 3.9 THERM120 THERM120M THERM120S Thermal 120 °C threshold Sense is 1 if above threshold Dual 3.9 THERM125 THERM125M THERM125S Thermal 125 °C threshold Sense is 1 if above threshold Dual 3.9 THERM130 THERM130M THERM130S Thermal 130 °C threshold Sense is 1 if above threshold Dual 3.9 SW1AFAULTI SW1AFAULTM SW1AFAULTS Regulator 1A overcurrent limit Sense is 1 if above current limit L to H 8.0 SW1BFAULTI SW1BFAULTM SW1BFAULTS Regulator 1B overcurrent limit Sense is 1 if above current limit L to H 8.0 SW2FAULTI SW2FAULTM SW2FAULTS Regulator 2 overcurrent limit Sense is 1 if above current limit L to H 8.0 SW3AFAULTI SW3AFAULTM SW3AFAULTS Regulator 3A overcurrent limit Sense is 1 if above current limit L to H 8.0 SW3BFAULTI SW3BFAULTM SW3BFAULTS Regulator 3B overcurrent limit Sense is 1 if above current limit L to H 8.0 SWBSTFAULTI SWBSTFAULTM SWBSTFAULTS SWBST overcurrent limit Sense is 1 if above current limit L to H 8.0 VGEN1FAULTI VGEN1FAULTM VGEN1FAULTS VGEN1 overcurrent limit Sense is 1 if above current limit L to H 8.0 |
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