MMPF0200 datasheet(29/114 Pages) NXP

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NXP Semiconductors

PF0200

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.4.2.1

Turn on events

From OFF and Sleep modes, the PMIC is powered on by a turn-on event. The type of Turn-on event depends on the configuration of

PWRON. PWRON may be configured as an active high when PWRON_CFG = 0, or as the input of a mechanical switch when

PWRON_CFG = 1. VIN must be greater than UVDET for the PMIC to turn-on. When PWRON is configured as an active high and PWRON

is high (pulled up to VSNVS) before VIN is valid, a VIN transition from 0.0 V to a voltage greater than UVDET is also a Turn-on event. See

the State diagram, Figure 8, and the Table 24 for more details. Any regulator enabled in the Sleep mode will remain enabled when

transitioning from Sleep to ON, i.e., the regulator will not be turned off and then on again to match the start-up sequence. The following

is a more detailed description of the PWRON configurations:

• If PWRON_CFG = 0, the PWRON signal is high and VIN > UVDET, the PMIC will turn on; the interrupt and sense bits, PWRONI and

PWRONS respectively, will be set.

• If PWRON_CFG = 1, VIN > UVDET and PWRON transitions from high to low, the PMIC will turn on; the interrupt and sense bits,

PWRONI and PWRONS respectively, will be set.

The sense bit will show the real time status of the PWRON pin. In this configuration, the PWRON input can be a mechanical switch

debounced through a programmable debouncer, PWRONDBNC[1:0], to avoid a response to a very short (i.e., unintentional) key press.

The interrupt is generated for both the falling and the rising edge of the PWRON pin. By default, a 30 ms interrupt debounce is applied to

both falling and rising edges. The falling edge debounce timing can be extended with PWRONDBNC[1:0] as defined in the table below.

The interrupt is cleared by software, or when cycling through the OFF mode.

6.4.2.2

Turn off events

PWRON pin

The PWRON pin is used to power off the PF0200. The PWRON pin can be configured with OTP to power off the PMIC under the following

two conditions:

1. PWRON_CFG bit = 0, SWxOMODE bit = 0 and PWRON pin is low.

2. PWRON_CFG bit = 1, SWxOMODE bit = 0, PWRONRSTEN = 1 and PWRON is held low for longer than 4.0 seconds.

Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.

Thermal protection

If the die temperature surpasses a given threshold, the thermal protection circuit will power off the PMIC to avoid damage. A turn-on event

will not power on the PMIC while it is in thermal protection. The part will remain in Off mode until the die temperature decreases below a

given threshold. There are no specific interrupts related to this other than the warning interrupt. See Power dissipation section for more

detailed information.

Undervoltage detection

When the voltage at VIN drops below the undervoltage falling threshold, UVDET, the state machine will transition to the Coin Cell mode.

Table 25. PWRON hardware debounce bit settings

Bits

State

Turn on

debounce (ms)

Falling edge INT

debounce (ms)

Rising edge INT

debounce (ms)

PWRONDBNC[1:0]

0.0

31.25

125

31.25

750

31.25

Notes

37.

The sense bit, PWRONS, is not debounced and follows the state of the PWRON pin.

MMPF0200 Datasheet(PDF) 29 Page - NXP Semiconductors

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