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MMPF0200 Datasheet(PDF) 84 Page - NXP Semiconductors

Part # MMPF0200
Description  12 channel configurable power management integrated circuit
PDF  114 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MMPF0200 Datasheet(HTML) 84 Page - NXP Semiconductors

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NXP Semiconductors
PF0200
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
A full description of all interrupt, mask, and sense registers is provided in Tables 101 to 112.
VGEN2FAULTI
VGEN2FAULTM
VGEN2FAULTS
VGEN2 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
VGEN3FAULTI
VGEN3FAULTM
VGEN3FAULTS
VGEN3 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
VGEN4FAULTI
VGEN4FAULTM
VGEN4FAULTS
VGEN4 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
VGEN5FAULTI
VGEN5FAULTM
VGEN1FAULTS
VGEN5 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
VGEN6FAULTI
VGEN6FAULTM
VGEN6FAULTS
VGEN6 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
OTP_ECCI
OTP_ECCM
OTP_ECCS
1 or 2 bit error detected in OTP registers
Sense is 1 if error detected
L to H
8.0
Notes
74.
Debounce timing for the falling edge can be extended with PWRONDBNC[1:0].
Table 101. Register INTSTAT0 - ADDR 0x05
Name
Bit #
R/W
Default
Description
PWRONI
0
R/W1C
0
Power on interrupt bit
LOWVINI
1
R/W1C
0
Low-voltage interrupt bit
THERM110I
2
R/W1C
0
110 °C Thermal interrupt bit
THERM120I
3
R/W1C
0
120 °C Thermal interrupt bit
THERM125I
4
R/W1C
0
125 °C Thermal interrupt bit
THERM130I
5
R/W1C
0
130 °C Thermal interrupt bit
UNUSED
7:6
–
00
Unused
Table 102. Register INTMASK0 - ADDR 0x06
Name
Bit #
R/W
Default
Description
PWRONM
0
R/W1C
1
Power on interrupt mask bit
LOWVINM
1
R/W1C
1
Low-voltage interrupt mask bit
THERM110M
2
R/W1C
1
110 °C Thermal interrupt mask bit
THERM120M
3
R/W1C
1
120 °C Thermal interrupt mask bit
THERM125M
4
R/W1C
1
125 °C Thermal interrupt mask bit
THERM130M
5
R/W1C
1
130 °C Thermal interrupt mask bit
UNUSED
7:6
–
00
Unused
Table 100. Interrupt, mask and sense bits (continued)
Interrupt
Mask
Sense
Purpose
Trigger
Debounce time (ms)



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