AD9154 datasheet(45/124 Pages) AD

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Data Sheet

AD9154

Rev. C | Page 45 of 124

TRANSPORT LAYER

DELAY

BUFFER 1

DELAY

BUFFER 0

F2S_0

F2S_1

DAC 1_I0[15:0]

DAC 2_Q0[15:0]

PCLK_1

LANE 0 OCTETS

LANE 7 OCTETS

PCLK_0

SPI CONTROL

LANE 3 OCTETS

LANE 4 OCTETS

DAC 3_I0[15:0]

DAC 4_Q0[15:0]

TRANSPORT LAYER

(QBD)

SPI CONTROL

Figure 57. Transport Layer Block Diagram

The transport layer receives the descrambled JESD204B frames

and converts them to DAC samples based on the programmed

JESD204B parameters shown in Table 42. A number of device

parameters are defined in Table 43.

Table 42. JESD204B Transport Layer Parameters

Parameter

Description

Number of octets per frame per lane: 1, 2, or 4.

Number of frames per multiframe.

K = 32 if F = 1, K = 16 or 32 otherwise.

Number of lanes per converter device (per link), as

follows.

1, 2, 4, or 8 (single link mode).

1, 2, or 4 (dual link mode).

Number of converters per device (per link), as follows.

1, 2, or 4 (single link mode).

1 or 2 (dual link mode).

Number of samples per converter, per frame: 1 or 2.

Table 43. JESD204B Device Parameters

Parameter

Description

Number of control words per device clock per link.

Not supported, must be 0.

Number of control bits per conversion sample. Not

supported, must be 0.

High density user data format. Used when samples

must be split across lanes. Set to 1 when F = 1,

otherwise 0.

Converter resolution = 16.

N Prime (N

ʹ)

Total number of bits per sample = 16.

Certain combinations of these parameters, called JESD204B

operating modes, are supported by the AD9154. See Table 44

and Table 45 for a list of supported modes, along with their

associated clock relationships.

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