AD9154 datasheet(74/124 Pages) AD

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AD9154

Data Sheet

Rev. C | Page 74 of 124

is completed and is valid.

user that the DAC PLL hit the upper or lower edge of its operating

band, respectively. If either of these bits are high, recalibrate the

DAC PLL by setting Register 0x083, Bit 7 to 0 and then 1.

DAC PLL IRQ

The DAC PLL lock and lost signals are available as IRQ events.

Use Register 0x01F, Bit 5 and Bit 4 to enable these signals, and

then use Register 0x023, Bit 5 and Bit 4 to read back their

statuses and reset the IRQ signals. See the Interrupt Request

Operation section.

LC VCO

6GHz

12GHz

4-BIT

PROGRAMMABLE,

INTEGRATED

LOOP FILTER

CHARGE

PUMP

PFD

80MHz

MAX

RETIMER

DOWN

fREF

30MHz

TO 1GHz

B COUNTER

N1 =

DIVIDE BY

1, 2, 4, 8, 16, 32

0.1mA TO 6.4mA

FO CAL

ALC CAL

CAL CONTROL BITS

VCO

LDO

MUX/SELECTABLE BUFFERS

÷2

DAC CLOCK

MAXIMUM FREQUENCY = 1.6GHz

NMUX = 4, 8, 16

÷2

÷4

÷8

÷16

Figure 78. Device Clock PLL Block Diagram

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