DSP56857 datasheet(308/662 Pages) FREESCALE

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ESSI Block Diagram

5685X Digital Signal Controller User Manual, Rev. 4

12-8

Freescale Semiconductor

When this signal is configured as a transmit data signal, it is always an output signal regardless of

the SCD1 bit value. As an output, it is fully synchronized with the other ESSI transmit data

signals (STD and SC0).

Note:

The source of the Transmitter 0 drive-enable signal is the STD_OEN signal.

12.3.2.4

ESSI Serial Control Signal 2 (SC2)

This pin is used for frame sync I/O and can be configured as either an input or an output pin. The

direction of this signal is determined by the SCD2 bit of the SCR4 register. The frame sync is

used by the transmitter to synchronize the transfer of data in Asynchronous mode. It is used by

both the receiver and transmitter in Synchronous mode. The frame sync signal can be one-bit, or

one-word in length. The start of the frame sync can occur one-bit before the transfer of data, or

right at the start of the data transfer.

12.3.2.5 ESSI Transmit Data (STD)

The STD signal is used for transmitting data from the TXSR0 serial Transmit Shift Register. STD

is an output pin when data is being transmitted from the TXSR0 Shift Register. The STD pin is

tri-stated after transmitting the last data bit when another data word does not follow immediately.

If a data word follows immediately within a full clock cycle, the STD pin is not tri-stated.

12.3.2.6 ESSI Receive Data (SRD)

The SRD signal receives serial data, then transfers the data to the ESSI Receive Data Shift

12.4 ESSI Block Diagram

The following figure illustrates the ESSI block diagram. It consists of five control registers to

set-up the port, one status register, separate transmit and receive circuits with FIFO registers, and

separate serial clock and frame sync generation for the transmit and receive sections.

DSP56857 Datasheet(PDF) 308 Page - Freescale Semiconductor, Inc