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DSP56857 Datasheet(PDF) 45 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 45 Page - Freescale Semiconductor, Inc |
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45 / 662 page  56800E Core Description 5685X Overview, Rev. 4 Freescale Semiconductor 1-13 1.4 56800E Core Description This section provides a brief overview of the 56800E core. For a more thorough description, please refer to the 56800E Core Reference Manual (DSP56800ERM). 1.4.1 Key Features The 56800E architecture provides a variety of features to enhance performance, reduce application cost, and ease product development. The architectural features making these benefits possible include: • Efficient 16-bit engine with dual Harvard architecture • 120 Million Instructions Per Second (MIPS) at 120MHz core frequency • Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • Four, 36-bit accumulators including extension bits • 16-bit bidirectional shifter • Parallel instruction set with unique addressing modes • Hardware DO and REP loops • Three internal address buses and one external address bus • Four internal data buses and one external data bus • Instruction set supports both digital signal controller and controller functions • Four hardware interrupt levels • Five software interrupt levels • Controller-style addressing modes and instructions for compact code • Efficient C Compiler and local variable support • Software subroutine and interrupt stack with depth limited only by memory • JTAG/Enhanced OnCE debug programming interface 1.4.2 56800E Core Enhancements The 56800E core architecture extends the 56800 family architecture. It is source-code compatible with 56800 devices and adds the following new features: • Byte and long data types, supplementing the 56800’s word data type • 24-bit data memory address space • 21-bit program memory address space • Two additional 24-bit pointer registers • Two additional 36-bit accumulator registers |
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