DSP56857 datasheet(50/662 Pages) FREESCALE

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56800E Core Description

5685X Digital Signal Controller User Manual, Rev. 4

1-18

Freescale Semiconductor

This bus structure supports up to three simultaneous 16-bit transfers. Any one of the following

can occur in a single clock cycle:

•

One instruction fetch

•

One read from data memory

•

One write to data memory

•

Two reads from data memory

•

One instruction fetch and one read from data memory

•

One instruction fetch and one write to data memory

•

One instruction fetch and two reads from data memory

An instruction fetch will take place on every clock cycle, although it is possible for data memory

accesses to be performed without an instruction fetch. Such accesses typically occur when a

hardware loop is executed and the repeated instruction is only fetched on the first loop iteration.

1.4.7 Data Arithmetic Logic Unit (Data ALU)

The data Arithmetic Logic Unit (ALU) performs all of the arithmetic, logical, and shifting

operations on data operands. The data ALU contains the following components:

•

Three, 16-bit data registers (X0, Y0, and Y1)

•

Four, 36-bit accumulator registers (A, B, C, and D)

•

One Multiply-Accumulator (MAC) unit

•

A single-bit accumulator shifter

•

One arithmetic and logical multi-bit shifter

•

One MAC output limiter

•

One data limiter

All in a single instruction cycle, the data ALU can perform multiplication,

multiply-accumulation, with positive or negative accumulation, addition, subtraction, shifting,

and logical operations. Division and normalization operations are provided by iteration

instructions. Signed and unsigned multi-precision arithmetic is also supported. All operations are

performed using two’s-complement fractional or integer arithmetic.

Data ALU source operands can be 8, 16, 32, or 36 bits in size and can be located in memory, in

immediate instruction data, or in the data ALU registers. Arithmetic operations and shifts can

have 16-, 32-, or 36-bit results. Logical operations are performed on 16- or 32-bit operands and

yield results of the same size. The results of data ALU operations are stored either in one of the

data ALU registers or directly in memory.

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