DSP56857 datasheet(47/662 Pages) FREESCALE

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56800E Core Description

5685X Overview, Rev. 4

Freescale Semiconductor

1-15

Complete architecture includes these components:

•

56800E core

•

On-chip program memory

•

On-chip data memory

•

On-chip peripherals

•

IPBus peripheral interface

•

External bus interface

Some 56800E devices might not implement an external bus interface. Regardless of the

implementation, all peripherals communicate with the 56800E core via the IPBus interface. The

IPBus interface standard connects the main data address bus XAB1, CDBR, and CDBW

unidirectional data buses to the corresponding bus interfaces on the peripheral devices. The

program memory buses are not connected to peripherals.

1.4.4 56800E Core Block Diagram

The 56800E core is composed of several independent functional units. The program controller,

Address Generation Unit (AGU), and data Arithmetic Logic Unit (ALU) contain their own

increases throughput. There is also an independent bit-manipulation unit enabling efficient

bit-manipulation operations. Each functional unit interfaces with the other units, memory, and the

memory-mapped peripherals over the core’s internal address and data buses. A block diagram of

the 56800E core architecture is shown in Figure 1-7.

DSP56857 Datasheet(PDF) 47 Page - Freescale Semiconductor, Inc