 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DSP56857 Datasheet(PDF) 572 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
DSP56857 Datasheet(HTML) 572 Page - Freescale Semiconductor, Inc |
|
|
572 / 662 page  Application: Date: Programmer: Sheet Appendix B - Programmer’s Sheets, Rev. 4 Freescale Semiconductor B-70 Preliminary ESSI Status Register (SSR) Bits Name Description 15 IF1 Input Flag 1 This bit is enabled only when SC1 is configured as an input flag and Synchronous mode is selected. If not enabled, the IF1 bit is cleared. 14 IF0 Input Flag 0 This bit is enabled only when SC0 is configured as an input flag and the Synchronous mode is selected. If it is not enabled, the IF0 bit is cleared. 12 TFF Transmit FIFO Full This status bit allows monitoring when the TTF is full. 0 Transmit FIFO can accept more data 1 Transmit FIFO is full 11 TLS Transmit Last Slot This status bit indicates timing of the last transmit slot during the Network mode operation 0 Not currently transmitting the last time slot of the transmit frame 1 Last slot of the transmit frame is currently being transmitted 10 RLS Receive Last Slot This status bit indicates the timing of the last receive slot during the Network mode operation 0 Not currently receiving the last time slot of the receive frame 1 Last slot of the receive frame is currently being received 9 TF1ERR Transmit FIFO 1 Error When the transmitter status control TXSF1 is set and the FIFOs are in use, this status bit will indicate the state of FIFO1 is not the same as FIFO0. 0 State of TXFIFO0 and TXFIFO1 contains the same amount of data 1 State of TXFIFO is different than the state of the TXFIFO1 8 TF2ERR Transmit FIFO 2 Error When the transmitter status control TXSF2 is set and FIFOs are in use, this status bit indicates the state of FIFO2 is not the same as FIFO0. 0 Status of TXFIFO2 matches the other enabled TXFIFOs 1 Status (data content level) of TXFIFO2 is different than the other enabled TXFIFOs ESSI Status Register (SSR) Base + $4 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read IF1 IF0 TFF TLS RLS TF1ERR TF2ERR RDR TDE ROE TUE TFS RFS RFF TFE Write Reset 000 000 0 0 00000 000 ESSI 3 of 16 denotes Reserved Bits See the following page for continuation of this register |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
