DSP56857 datasheet(157/662 Pages) FREESCALE

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OSC (Oscillator) Circuit Detail

On-Chip Clock Synthesis (OCCS), Rev. 4

Freescale Semiconductor

6-7

6.2.3 Using an External Active Clock Source Above 4 MHz

When using an external active clock source of a higher frequency than 4MHz (up to 240MHz is

allowable) the settings detailed below should be used.

Figure 6-5. Using an External Active High Frequency Clock, > 4 MHz

Since the differential amplifier is band limited to just over 4MHz, in this example the default

TIME_CLK path’s divide by 128 counter will no longer have an adequate signal for proper

operation. Instead, the user programmable divide by circuit should be used. This requires correct

setting of both the CGMCR[TOD] and [TOD_SEL] register fields as shown in the figure.

In this particular example, the externally applied clock, and hence Fref, are running at 30 MHz.

This requires TOD_SEL be set to 1 and the TOD register set to 480. The input frequency of

30MHz divided down by 480 and then again by a fixed value of 2 yields the desired 31.25KHz

TIME_CLK frequency.

Note:

With the CGMCR register’s TOD_SEL field set to 1, EXTAL can be tied to ground (as

shown), to mid-rail, or high. The optimal connection of EXTAL is to ground.

6.2.4 STOP Mode Features

In an attempt to conserve power, applications may power the device down by executing STOP or

WAIT instructions. The DSP5685x OCCS module supports three variants of STOP mode

processing.

1. Case where CGMCR[TOD_SEL] = 0

A STOP instruction will result in the MSTR_CLK clock source being forced back to Fref

and the PLL being powered down (PLL_SHUTDOWN asserts. If CGMCR[TOD_SEL] is

0, then OSC_LOWPWR will assert, bringing the OSC module into its lowest power alive

state. Only the inverter, differential amplifier and the fixed divide-by 128 block remain

EXTAL

CGMCR[TOD_SEL] = 1

Note (1)

Fref

(30 MHz)

TIME_CLK (31.25 KHz)

XTAL

128

(1)

OSC_LOPWR

Notes (1)

Ftime

(invalid signal)

BOLD represents default states and typical

conditions.

1) See STOP Mode Features for further details

CGMCR[TOD] = 480

High Frequency Digital Clock

(30 MHz)

The amplifier’s bandwidth is limited to 4 MHz, so its

output is invalid in a High Frequency input scenario.

CGMCR[TOD] must be set to 1 and the CGMCR[TOD]

divider must be set to a reasonable value in order to

enable a valid TIME_CLK signal.

DSP56857 Datasheet(PDF) 157 Page - Freescale Semiconductor, Inc

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