STM32WB55CC datasheet(50/165 Pages) STMICROELECTRONICS

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Functional overview

STM32WB55xx

50/165

DS11929 Rev 3

3.23

Universal synchronous/asynchronous receiver transmitter

(USART)

The STM32WB55xx devices feature one universal synchronous receiver transmitter.

This interface provides asynchronous communication, IrDA SIR ENDEC support,

multiprocessor communication mode, single-wire half-duplex communication mode and has

LIN Master/Slave capability. It provides hardware management of the CTS and RTS signals,

and RS485 Driver Enable.

The USART is able to communicate at speeds of up to 4 Mbit/s, and also provides Smart

Card mode (ISO 7816 compliant) and SPI-like communication capability.

The USART supports synchronous operation (SPI mode), and can be used as an SPI

master.

The USART has a clock domain independent from the CPU clock, allowing the it to wake up

the MCU from Stop mode using baudrates up to 200 Kbaud.The wake up events from Stop

mode are programmable and can be:

•

Start bit detection

•

Any received data frame

•

A specific programmed data frame

The USART interface can be served by the DMA controller.

3.24

Low-power universal asynchronous receiver transmitter

(LPUART)

The device embeds two Low-Power UARTs, enabling asynchronous serial communication

with minimum power consumption. The LPUARTs support half duplex single wire

communication and modem operations (CTS/RTS), allowing multiprocessor

communication.

The two LPUARTs have a clock domain independent from the CPU clock, and can wakeup

the system from Stop mode using baudrates up to 220 Kbaud. The wake up events from

Stop mode are programmable and can be:

•

Start bit detection

•

Any received data frame

•

A specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600

baud. Therefore, even in Stop mode, the LPUARTs can wait for an incoming frame while

Independent clock

Wakeup from Stop 0 / Stop 1 mode on address match

Wakeup from Stop 2 mode on address match

1. X: supported

Table 14. I2C implementation (continued)

I2C features(1)

I2C1

I2C3

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