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STM32WB55CC Datasheet(PDF) 18 Page - STMicroelectronics

Part # STM32WB55CC
Description  Multiprotocol wireless 32-bit MCU Arm
PDF  165 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WB55CC Datasheet(HTML) 18 Page - STMicroelectronics

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Functional overview
STM32WB55xx
18/165
DS11929 Rev 3
•
Write protection (WRP): the protected area is protected against erasing and
programming. Two areas can be selected, with 4 Kbyte granularity.
•
Proprietary code readout protection (PCROP): two parts of the Flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU, as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
Two areas can be selected, with 2 KByte granularity. An additional option bit
(PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP
protection is changed from Level 1 to Level 0.
A section of the Flash memory is secured for the RF subsystem CPU2, and cannot be
accessed by the host CPU1.
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
•
single error detection and correction
•
double error detection
•
the address of the ECC fail can be read in the ECC register
The embedded Flash memory is shared between CPU1 and CPU2 on a time sharing basis.
A dedicated HW mechanism allows both CPUs to perform Write/Erase operations.
Table 3. Access status vs. readout protection level and execution modes
Area
Protection
level
User execution
Debug, boot from SRAM or boot
from system memory (loader)
Read
Write
Erase
Read
Write
Erase
Main
memory
1
Yes
Yes
Yes
No
No
No
2
Yes
Yes
Yes
N/A
N/A
N/A
System
memory
1
Yes
No
No
Yes
No
No
2
Yes
No
No
N/A
N/A
N/A
Option
bytes
1
Yes
Yes
Yes
Yes
Yes
Yes
2Yes
No(1)
1. The option byte can be modified by the RF subsystem.
No(1)
N/A
N/A
N/A
Backup
registers
1Yes
Yes
N/A(2)
2. Erased when RDP changes from Level 1 to Level 0.
No
No
N/A(2)
2
Yes
Yes
N/A
N/A
N/A
N/A
SRAM2a
SRAM2b
1
Yes
Yes
Yes(2)
No
No
No(2)
2
Yes
Yes
Yes
N/A
N/A
N/A



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