STM32WB55CC datasheet(51/165 Pages) STMICROELECTRONICS

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DS11929 Rev 3

51/165

STM32WB55xx

Functional overview

having an extremely low energy consumption. Higher speed clock can be used to reach

higher baudrates.

The LPUART interfaces can be served by the DMA controller.

3.25

Serial peripheral interface (SPI1, SPI2)

Two SPI interfaces allow communication up to 32 Mbit/s in master and up to 24 Mbit/s in

slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8

master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI

interfaces support NSS pulse mode, TI mode and Hardware CRC calculation.

All SPI interfaces can be served by the DMA controller.

3.26

Serial audio interfaces (SAI1)

The device embeds a dual channel SAI peripheral that supports full duplex audio operation.

The SAI bus interface handles communications between the microcontroller and the serial

audio protocol.

The SAI peripheral supports:

•

One independent audio sub-block that can be a transmitter or a receiver, with the

respective FIFO

•

8-word integrated FIFOs

•

Synchronous or asynchronous mode

•

Master or slave configuration

•

Clock generator to target independent audio frequency sampling when audio sub-block

is configured in master mode

•

Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit

•

Peripheral with large configurability and flexibility allowing to target as example the

following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF

out

•

Up to 16 slots available with configurable size and with the possibility to select which

ones are active in the audio frame

•

Number of bits by frame may be configurable

•

Frame synchronization active level configurable (offset, bit length, level)

•

First active bit position in the slot is configurable

•

LSB first or MSB first for data transfer

•

Mute mode

•

Stereo/Mono audio frame capability

•

Communication clock strobing edge configurable (SCK)

•

Error flags with associated interrupts if enabled respectively

–

Overrun and underrun detection

–

Anticipated frame synchronization signal detection in slave mode

–

Late frame synchronization signal detection in slave mode

–

Codec not ready for the AC’97 mode in reception

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