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STM32WB55CC Datasheet(PDF) 69 Page - STMicroelectronics |
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STM32WB55CC Datasheet(HTML) 69 Page - STMicroelectronics |
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69 / 165 page  DS11929 Rev 3 69/165 STM32WB55xx Memory mapping 69 5 Memory mapping The STM32WB55xx devices feature a single physical address space that can be accessed by the application processor and by the RF subsystem. A part of the Flash memory and of the SRAM2a and SRAM2b memories are made secure, exclusively accessible by the CPU2, protected against execution, read and write from CPU1 and DMA. In case of shared resources the SW should implement arbitration mechanism to avoid access conflicts. This happens for peripherals Reset and Clock Controller (RCC), Power Controller (PWC), EXTI and Flash interface, and can be implemented using the built-in semaphore block (HSEM). By default the RF subsystem and CPU2 operate in secure mode. This implies that part of the Flash and of the SRAM2 memories can only be accessed by the RF subsystem and by the CPU2. In this case the Host processor (CPU1) has no access to these resources. The detailed memory map and the peripheral mapping of the STM32WB55xx devices can be found in the reference manual RM0434. |
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