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STM32WB55CC Datasheet(PDF) 63 Page - STMicroelectronics |
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STM32WB55CC Datasheet(HTML) 63 Page - STMicroelectronics |
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63 / 165 page ![]() DS11929 Rev 3 63/165 STM32WB55xx Pinouts and pin description 69 46 66 F5 PB6 I/O FT_fla - LPTIM1_ETR, I2C1_SCL, USART1_TX, TSC_G2_IO3, LCD_SEG6, SAI1_FS_B, TIM16_CH1N, MCO, CM4_EVENTOUT COMP2_INP 47 67 D7 PB7 I/O FT_fla - LPTIM1_IN2, TIM1_BKIN, I2C1_SDA, USART1_RX, TSC_G2_IO4, LCD_SEG21, TIM17_CH1N, CM4_EVENTOUT COMP2_INM, PVD_IN - - B9 VSS S - - - - 48 68 A10 VDD S - - - - - - C8 PE0 I/O FT_l - TIM1_ETR, TSC_G7_IO3, LCD_SEG36, TIM16_CH1, CM4_EVENTOUT - - - B10 PE1 I/O FT_l - TSC_G7_IO2, LCD_SEG37, TIM17_CH1, CM4_EVENTOUT - 1. PC13, PC14 and PC15 are supplied through the power switch. As this switch only sinks a limited amount of current (3 mA), the use of the PC13, PC14 and PC15 GPIOs in output mode is limited: - the speed should not exceed 2 MHz with a maximum load of 30 pF - these GPIOs must not be used as current sources (e.g. to drive an LED). 2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the reference manual RM0351, available on www.st.com. 3. On UFQFPN48 VDDA is connected to VREF+. 4. RF pin, use the nominal PCB layout. 5. 32 MHz oscillator pins, use the nominal PCB layout according to reference design (see AN5165). 6. Reserved for production, must be kept unconnected. 7. High frequency (above 100 KHz) may impact the RF performances. 8. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13 and PB4 pins and the internal pull-down on PA14 pin are activated. Table 16. STM32WB55xx pin and ball definitions (continued) Pin number Pin name (function after reset) Alternate functions Additional functions |
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