STM32WB55CC datasheet(30/165 Pages) STMICROELECTRONICS

30 / 165 page

Functional overview

STM32WB55xx

30/165

DS11929 Rev 3

periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE, or

from the RF system wakeup).

The system clock after wakeup is 16 MHz, derived from the HSI16. If used, the SMPS

is restarted automatically.

In this mode the RF can be used.

•

Shutdown

The Shutdown mode allows to achieve the ultimate lowest power consumption. The

internal regulator is switched off so that the VCORE domain is powered off.

The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible

in this mode, therefore the switch to Backup domain is not supported.

SRAM1, SRAM2a, SRAM2b and register contents are lost except for registers in the

Backup domain.

The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin

event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic

wakeup, timestamp, tamper).

The system clock after wakeup is 4 MHz, derived from the MSI.

In this mode the RF is no longer operational.

When the RF subsystem is active, it will change the power state according to its needs

(Run, Stop, Standby). This operation is transparent for the CPU1 host application and

managed by a dedicated HW state machine. At any given time the effective power state

reached is the higher one needed by both the CPU1 and RF sub-system.

Table 7 summarizes the peripheral features over all available modes. Wakeup capability is

detailed in gray cells.

Table 7. Features over all modes(1)

Peripheral

Stop0/Stop1

Stop 2

Standby Shutdown

CPU1

CPU2

Radio System

(BLE, 802.15.4)

YY(2)

Y-

YY(3) Y(3)

Flash memory (up to 1 MB)

Y (4)

YO(5) O(5)

-R

SRAM1 (up to 192 KB)

Y(6)

YY(6)

-R

SRAM2a (32 KB)

Y(6)

YY(6)

-R

-R(7)

SRAM2b (32 KB)

Y(6)

YY(6)

-R

Quad-SPI

Backup Registers

-R

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