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HD64F2145 Datasheet(PDF) 348 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 348 Page - Renesas Technology Corp |
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348 / 829 page ![]() Rev. 2.0, 08/02, page 308 of 788 Bit Bit Name Initial Value R/W Description 2PREQF 0 R/(W)* 1 Pre-Equalization Flag Detects the occurrence of an IHI signal 2fH modification condition. The generation of a falling/rising edge in the IHI signal during a mask interval is expressed as the occurrence of a 2fH modification condition. For details, see section 13.4.4, 2fH Modification of IHI Signal. [Clearing condition] When 0 is written in PREQF after reading PREQF = 1 [Setting condition] When an IHI signal 2fH modification condition is detected 1 IHI Undefined* 2 R IHI Signal Level Indicates the current level of the IHI signal. Signal source and phase inversion selection for the IHI signal depends on the contents of TCONRI. Read this bit to determine whether the input signal is positive or negative, then maintain the IHI signal at positive phase by modifying TCONRI. 0: The IHI signal is low 1: The IHI signal is high 0 IVI Undefined* 2 R IVI Signal Level Indicates the current level of the IVI signal. Signal source and phase inversion selection for the IVI signal depends on the contents of TCONRI. Read this bit to determine whether the input signal is positive or negative, then maintain the IVI signal at positive phase by modifying TCONRI. 0: The IVI signal is low 1: The IVI signal is high Notes: 1. Only 0 can be written, to clear the flag. 2. The initial value is undefined since it depends on the pin state. |
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