HD64F2145 datasheet(67/829 Pages) RENESAS

67 / 829 page

Rev. 2.0, 08/02, page 27 of 788

Section 2 CPU

The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that

is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit

general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.

This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending

on the product. For details on each product, refer to section 3, MCU Operating Modes.

2.1

Features

• Upward-compatibility with H8/300 and H8/300H CPUs

Can execute H8/300 CPU and H8/300H CPU object programs

• General-register architecture

Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers

• Sixty-five basic instructions

8/16/32-bit arithmetic and logic instructions

Multiply and divide instructions

Powerful bit-manipulation instructions

• Eight addressing modes

Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]

Immediate [#xx:8, #xx:16, or #xx:32]

Program-counter relative [@(d:8,PC) or @(d:16,PC)]

Memory indirect [@@aa:8]

• 16-Mbyte address space

Program: 16 Mbytes

Data: 16 Mbytes

• High-speed operation

All frequently-used instructions are executed in one or two states

8/16/32-bit register-register add/subtract: 1 state

× 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)

÷ 8-bit register-register divide: 12 states (DIVXU.B)

× 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)

÷ 16-bit register-register divide: 20 states (DIVXU.W)

CPU210A_010020020700

HD64F2145 Datasheet(PDF) 67 Page - Renesas Technology Corp