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HD64F2145 Datasheet(PDF) 92 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 92 Page - Renesas Technology Corp |
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92 / 829 page ![]() Rev. 2.0, 08/02, page 52 of 788 op op rn rm NOP, RTS ADD.B Rn, Rm MOV.B @(d:16, Rn), Rm rn rm op EA (disp) op cc EA (disp) BRA d:16 (1) Operation field only (2) Operation field and register fields (3) Operation field, register fields, and effective address extension (4) Operation field, effective address extension, and condition field Figure 2.11 Instruction Formats (Examples) 2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic operations instructions can use the register direct and immediate addressing modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions can use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes No. Addressing Mode Symbol 1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn) 4 Register indirect with post-increment Register indirect with pre-decrement @ERn+ @–ERn 5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 Immediate #xx:8/#xx:16/#xx:32 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 8 Memory indirect @@aa:8 |
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