HD64F2145 datasheet(14/829 Pages) RENESAS

14 / 829 page

Rev. 2.0, 08/02, page xii of xxxviii

8.11.2 Port A Output Data Register (PAODR) ...............................................................192

8.11.3 Port A Input Data Register (PAPIN) ....................................................................193

8.11.4 Pin Functions........................................................................................................193

8.11.5 Port A Input Pull-Up MOS...................................................................................197

8.12

Port B ................................................................................................................................198

8.12.1 Port B Data Direction Register (PBDDR)............................................................198

8.12.2 Port B Output Data Register (PBODR)................................................................199

8.12.3 Port B Input Data Register (PBPIN) ....................................................................199

8.12.4 Pin Functions........................................................................................................200

8.12.5 Port B Input Pull-Up MOS...................................................................................202

8.13

Additional Overview for H8S/2160B and H8S/2161B .....................................................203

8.14

Ports C, D ..........................................................................................................................204

8.14.1 Port C and Port D Data Direction Registers (PCDDR, PDDDR).........................205

8.14.2 Port C and Port D Output Data Registers (PCODR, PDODR).............................206

8.14.3 Port C and Port D Input Data Registers (PCPIN, PDPIN) ...................................207

8.14.4 Port C and Port D Nch-OD Control Register (PCNOCR, PDNOCR)..................208

8.14.5 Pin Functions........................................................................................................208

8.14.6 Input Pull-Up MOS in Ports C and D...................................................................209

8.15

Ports E, F ...........................................................................................................................209

8.15.1 Port E and Port F Data Direction Registers (PEDDR, PFDDR) ..........................210

8.15.2 Port E and Port F Output Data Registers (PEODR, PFODR) ..............................211

8.15.3 Port E and Port F Input Data Registers (PEPIN, PFPIN) .....................................212

8.15.4 Port E and Port F Nch-OD Control Register (PENOCR, PFNOCR) ...................213

8.15.5 Pin Functions........................................................................................................213

8.15.6 Input Pull-Up MOS in Ports E and F ...................................................................214

8.16

Port G ..................................................................................................................... ...........214

8.16.1 Port G Data Direction Register (PGDDR) ...........................................................214

8.16.2 Port G Output Data Register (PGODR) ...............................................................215

8.16.3 Port G Input Data Register (PGPIN) ....................................................................215

8.16.4 Port G Nch-OD Control Register (PGNOCR) .....................................................216

8.16.5 Pin Functions........................................................................................................216

Section 9 8-Bit PWM Timer (PWM) ................................................................ 217

9.1

Features .............................................................................................................................217

9.2

Input/Output Pin ................................................................................................................219

9.3

Register Descriptions ........................................................................................................219

9.3.1

PWM Register Select (PWSL) .............................................................................220

9.3.2

PWM Data Registers (PWDR0 to PWDR15) ......................................................222

9.3.3

PWM Data Polarity Registers A and B (PWDPRA, PWDPRB)..........................222

9.3.4

PWM Output Enable Registers A and B (PWOERA, PWOERB) .......................223

9.3.5

Peripheral Clock Select Register (PCSR).............................................................224

9.4

Operation...........................................................................................................................225

9.5

Usage Note ........................................................................................................................226

HD64F2145 Datasheet(PDF) 14 Page - Renesas Technology Corp

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