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HD64F2145 Datasheet(PDF) 101 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 101 Page - Renesas Technology Corp |
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101 / 829 page ![]() Rev. 2.0, 08/02, page 61 of 788 Prior to executing BCLR: P47 P46 P45 P44 P43 P42 P41 P40 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level DDR 001 111 11 DR 100 000 00 BCLR instruction executed: BCLR #0, @P4DDR The BCLR instruction is executed for DDR in port 4. After executing BCLR: P47 P46 P45 P44 P43 P42 P41 P40 Input/output Output Output Output Output Output Output Output Input Pin state Low level High level Low level Low level Low level Low level Low level High level DDR 1 11 111 1 0 DR 1 0 0 000 0 0 Operation: 1. When the BCLR instruction is executed, first the CPU reads P4DDR. Since P4DDR is a write-only register, so the CPU reads H’FF. In this example P4DDR has a value of H'3F, but the value read by the CPU is H'FF. 2. The CPU clears bit 0 of the read data to 0, changing data to H'FE. 3. The CPU writes H'FE to DDR, completing execution of BCLR. As a result of the BCLR instruction, bit 0 in DDR is set to 0, and P40 becomes an input pin. However, bits 7 and 6 of DDR are modified to 1, therefore P47 and P46 become output pins. |
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