HD64F2145 datasheet(106/829 Pages) RENESAS

106 / 829 page

Rev. 2.0, 08/02, page 66 of 788

Bit

Bit Name

Initial Value

R/W

Description

NMIEG

R/W

NMI Edge Select

Selects the valid edge of the NMI interrupt input.

0: An interrupt is requested at the falling edge of NMI

input

1: An interrupt is requested at the rising edge of NMI

input

HIE

R/W

Host Interface Enable

Controls CPU access to the host interface registers

(HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2),

the keyboard matrix interrupt and MOS input pull-up

control registers (KMIMR, KMPCR, and KMIMRA), the

8-bit timer (TMR_X and TMR_Y) registers

(TCR_X/TCR_Y, TCSR_X/TCSR_Y,

TICRR/TCORA_Y, TICRF/TCORB_Y,

TCNT_X/TCNT_Y, TCORC/TISR, TCORA_X, and

TCORB_X), and the timer connection registers

(TCONRI, TCONRO, TCONRS, and SEDGR).

0: In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC

to H'(FF)FFFF, CPU access to 8-bit timer (TMR_X and

TMR_Y) registers and timer connection registers is

permitted

1: In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC

to H'(FF)FFFF, CPU access to host interface registers

and keyboard matrix interrupt and MOS input pull-up

control registers is permitted

RAME

R/W

RAM Enable

Enables or disables on-chip RAM. The RAME bit is

initialized when the reset state is released.

0: On-chip RAM is disabled

1: On-chip RAM is enabled

HD64F2145 Datasheet(PDF) 106 Page - Renesas Technology Corp

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