EMC1812 datasheet(17/102 Pages) MICROCHIP

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5.4

Limit Register Interaction

The various Limit registers in the device interact based on both external conditions present on the diode

pins, as well as changes in register bits in the I2C interface.

5.4.1

High Limit Register

The High Limit Status register contains the Status bits that are set when a temperature channel high limit

is exceeded. If any of these bits are set, then the HIGH Status bit in the STATUS register is set. Reading

from the High Limit Status register clears all bits. Reading from the register will also clear the HIGH

Status bit in the STATUS register.

The ALERT pin will be set if the programmed number of consecutive alert counts has been met and any

of these Status bits are set.

The Status bits remain set until a read is performed, unless the ALERT pin is configured as a comparator

output (see 5.5.2 ALERT/THERM2 Pin in Therm Mode).

5.4.2

Low Limit Register

The Low Limit Status register contains the Status bits that are set when a temperature channel drops

below the low limit. If any of these bits are set, then the LOW Status bit in the STATUS register is set.

Reading from the Low Limit Status register clears all bits.

The ALERT pin will be set if the programmed number of consecutive alert counts has been met and any

of these Status bits are set.

The Status bits will remain set until a read is performed, unless the ALERT pin is configured as a

comparator output (see 5.5.2 ALERT/THERM2 Pin in Therm Mode).

5.4.3

THERM Limit Register

The Therm Limit registers are used to determine whether a critical thermal event has occurred. If the

measured temperature exceeds the therm limit, the THERM pin is asserted. The limit setting must match

the chosen data format of the temperature reading registers.

Unlike the ALERT pin, the THERM pin cannot be masked. Additionally, the THERM pin is released once

the temperature drops below the corresponding threshold, minus the Therm Hysteresis.

5.5

ALERT/THERM2 Output

The ALERT/THERM2 pin is an open-drain output and requires a pull-up resistor to VDD and has two

modes of operation: Interrupt mode and Comparator mode. The mode of the ALERT/THERM2 output is

selected through the ALERT/THERM2 bit (see CONFIG, Address 03h).

5.5.1

ALERT/THERM2 Pin Interrupt Mode

When configured to operate in Interrupt mode, the ALERT/THERM2 pin asserts low when an out-of-limit

measurement (less than or equal to the low limit or greater than the high limit) is detected on any diode or

when a Diode Fault is detected. The ALERT/THERM2 pin will remain asserted as long as an out-of-limit

condition remains. Once the out-of-limit condition has been removed, the ALERT/THERM2 pin remains

asserted until the appropriate Status bits are cleared.

The ALERT/THERM2 pin can be masked by setting the MASK_ALL bit. Once the ALERT/THERM2 pin

has been masked, it is deasserted and remains as such until the MASK_ALL bit is cleared by the user.

Any interrupt conditions that occur while the ALERT/THERM2 pin is masked causes the STATUS register

to be updated normally. There are also individual channel masks (see 6.10.20 DIODE FAULT MASK.)

Multi-Channel Low-Voltage Remote Di...

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Datasheet

DS20005751A-page 17

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