ASL4501SHN datasheet(27/43 Pages) NXP

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ASL4501SHN

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Product data sheet

Rev. 2 — 10 January 2018

27 of 43

NXP Semiconductors

ASL4501SHN

Four-phase boost converter

During the SPI data transfer, the identifier byte and the actual content of the addressed

registers is returned via the SDO pin. The same happens for pure read accesses. Here

the read-only bit must be set on logic 1. The content of the data bytes that are transmitted

to the ASL4501SHN is ignored.

The ASL4501SHN monitors the number of data bits that are transmitted. If the number is

not 16, or a multiple of 16, then a write access is ignored and the SPI error indication bit is

set.

8.11.2 Typical use case illustration (write/read)

Consider a daisy chain scheme with one master connected to four slaves in daisy chain

fashion. The following commands are performed during one sequence (first sequence):

• Write data FFh to the register 1Ah slave 1

• Read from register 02h of slave 2

• Write data AFh to the register 2Fh of slave 3

• Read from register 44h of slave 4

Fig 11. Physical parallel slave connection

aaa-024031

SDI

ASL4501SHN

CSB

SDO

SCLK

SDI

ASLxxxxSHN

CSB

SDO

SCLK

SDI

ASLxxxxSHN

CSB

SDO

SCLK

µC

CSB1

MOSI

SCLK

SOMI

CSB2

CSB3

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