ASL4501SHN datasheet(42/43 Pages) NXP

42 / 43 page

ASL4501SHN

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 10 January 2018

42 of 43

NXP Semiconductors

ASL4501SHN

Four-phase boost converter

19. Tables

Table 1.

Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 2.

Pin description[1] . . . . . . . . . . . . . . . . . . . . . . . .4

Table 3.

Operating modes . . . . . . . . . . . . . . . . . . . . . . . .7

Table 4.

Internal phase control enable for phase logic 1

(address 0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 5.

Internal phase control enable for phase logic 2

(address 0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 6.

Gate driver output (address 02h) . . . . . . . . . . .10

Table 7.

Gate driver phase (address 0Fh) . . . . . . . . . . .10

Table 8.

Phase selection configuration (address 10h) . .10

Table 9.

Gate driver enable (address 01h) . . . . . . . . . .12

Table 10. Clock divider for Vout1 (address 09h) . . . . . . .13

Table 11. Clock divider for Vout2 (address 0Ah) . . . . . . .13

Table 12. Phase-off time and phase delay of output 1

(address 0Dh) . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 13. Phase-off time and phase delay of output 2

(address 0Eh) . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 14. Loop filter proportional configuration

(address 11h) . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 15. Loop filter integral configuration (address 12h) 14

Table 16. Slope compensation configuration

(address 13h) . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 17. Current sense slope resistor configuration

(address 14h) . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 18. Output voltage 1 register (address 03h) . . . . .15

Table 19. Output voltage 2 register (address 04h) . . . . .15

Table 20. Limit voltage output 1 register (address 05h) .16

Table 21. Limit voltage output 2 register (address 06h) .16

Table 22. Maximum phase current Vout1 register

(address 07h) . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 23. Maximum phase current Vout2 register

(address 08h) . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 24. Function control register (address 00h) . . . . . 17

Table 25. CSB count register 1 (address 41h) . . . . . . . . 18

Table 26. CSB count register 2 (address 42h) . . . . . . . . 19

Table 27. Calibration/frequency trimming register

(address 1Ch) . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 28. Calib/Ftrim settings . . . . . . . . . . . . . . . . . . . . . 20

Table 29. Calibration result register (address 4Ch) . . . . 20

Table 30. VGG control register (address 15h) . . . . . . . . 21

Table 31. Battery voltage register (address 45h) . . . . . . 22

Table 32. Undervoltage threshold register

(address 1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 33. Overvoltage threshold register (address 1Ah) 22

Table 34. Junction temperature register (address 46h) . 22

Table 35. Diagnostic register (address 5Fh) . . . . . . . . . . 23

Table 36. SPI frame format for a transition to the device 25

Table 37. SPI frame format for a transition from the

device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 38. Grouping of the register space. . . . . . . . . . . . . 29

Table 39. Control register group overview . . . . . . . . . . . . 29

Table 40. Configuration register group overview . . . . . . . 30

Table 41. Internal register group . . . . . . . . . . . . . . . . . . . 31

Table 42. Diagnostic register group overview . . . . . . . . . 31

Table 43. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 44. Thermal characteristics . . . . . . . . . . . . . . . . . . 32

Table 45. Static characteristics . . . . . . . . . . . . . . . . . . . . 33

Table 46. Dynamic characteristics . . . . . . . . . . . . . . . . . 35

Table 47. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 39

20. Figures

Fig 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Fig 2.

Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 3.

State diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Fig 4.

Boost converter phase circuit . . . . . . . . . . . . . . . .8

Fig 5.

Mapping of virtual phases (V1_1 to V2_4) to

physical phases (G1 to G4) . . . . . . . . . . . . . . . . . .9

Fig 6.

Phase control generator . . . . . . . . . . . . . . . . . . .12

Fig 7.

Frequency trimming flow . . . . . . . . . . . . . . . . . . .18

Fig 8.

SPI timing protocol. . . . . . . . . . . . . . . . . . . . . . . .25

Fig 9.

SPI frame format . . . . . . . . . . . . . . . . . . . . . . . . .25

Fig 10. Daisy chain configuration. . . . . . . . . . . . . . . . . . .26

Fig 11. Physical parallel slave connection . . . . . . . . . . . .27

Fig 12. SPI frame format . . . . . . . . . . . . . . . . . . . . . . . . .28

Fig 13. SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . .36

Fig 14. ASL4501SHN, configured as four-phase, single

output boost converter . . . . . . . . . . . . . . . . . . . . .37

Fig 15. Package outline SOT617-12 (HVQFN32) . . . . . .38

ASL4501SHN Datasheet(PDF) 42 Page - NXP Semiconductors

ASL4501SHN Datasheet(HTML) 42 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Datasheet Download

Link URL