ATTINY817-MFR. datasheet(37/492 Pages) MICROCHIP

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The program memory bus is connected to Flash, and the first program memory Flash address is 0x0000.

The data memory space is divided into I/O registers, SRAM, EEPROM and Flash.

All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is

referred to as the I/O memory space. The lowest 64 addresses are accessed directly with single cycle

IN/OUT instructions, or as the data space locations from 0x00 to 0x3F. These addresses can also be

accessed using load (LD/LDS/LDD) and store (ST/STS/STD) instructions. The lowest 32 addresses can

even be accessed with single cycle SBI/CBI instructions and SBIS/SBIC instructions. The rest is the

extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as

data space locations using load and store instructions.

Data addresses 0x1000 to 0x1800 are reserved for memory mapping of fuses, the NVM controller and

EEPROM. The addresses from 0x1800 to 0x7FFF are reserved for other memories, such as SRAM.

The Flash is mapped in the data space from 0x8000 and above. The Flash can be accessed with all load

and store instructions by using addresses above 0x8000. The LPM instruction accesses the Flash as in

the code space, where the Flash starts at address 0x0000.

For a summary of all AVR instructions, refer to the Instruction Set Summary. For details of all AVR

instructions, refer to http://www.microchip.com/design-centers/8-bit.

Related Links

NVMCTRL - Non Volatile Memory Controller

Memories

Instruction Set Summary

8.4

ALU - Arithmetic Logic Unit

The Arithmetic Logic Unit supports arithmetic and logic operations between registers, or between a

constant and a register. Single-register operations can also be executed.

The ALU operates in direct connection with all 32 general purpose registers. Arithmetic operations

between general purpose registers or between a register and an immediate are executed in a single clock

cycle, and the result is stored in the register file. After an arithmetic or logic operation, the Status register

(CPU.SREG) is updated to reflect information about the result of the operation.

ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and

16-bit arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit

arithmetic. The hardware multiplier supports signed and unsigned multiplication and fractional format.

8.4.1

Hardware Multiplier

The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier

supports different variations of signed and unsigned integer and fractional numbers:

•

Multiplication of signed/unsigned integers

•

Multiplication of signed/unsigned fractional numbers

•

Multiplication of a signed integer with an unsigned integer

•

Multiplication of a signed fractional number with an unsigned one

A multiplication takes two CPU clock cycles.

ATtiny417/817

Datasheet Complete

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