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W5100S Datasheet(PDF) 94 Page - WIZnet Co., Ltd |
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W5100S Datasheet(HTML) 94 Page - WIZnet Co., Ltd |
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94 / 110 page  94 / 110 W5100S Datasheet Version1.2.5 5.2 Parallel Bus Mode When MOD [3:0] is “010X”, W5100S connected to HOST via Parallel Bus Interface as shown in Figure 20. Figure 20 Direct & Indirect Mode Control by Host Parallel Bus Interface accesses COMMON/SOCKET Register and TX/RX Memory Block of W5100S through Register in Table 7. And also Parallel Bus Interface supports N-byte sequential Data Read/Write. Table 7 Indirect Mode Address Value ADDR[1:0] Symbol Description 00 MR Common Register MR 01 IDM_ARH Upper 8 bits Offset Address Register 10 IDM_ARL Lower 8 bits Offset Address Register 11 IDM_DR 8 Bits Data Register 5.2.1 Parallel Bus Data Write N-byte Date write Frame, as Shown in Figure 21. RDn DATA [7:0] WRn 1 ADDR [1:0] CSn 2 3 ADDRH ADDRL DATA 3 3 3 DATA DATA DATA Figure 21 Parallel Bus N-Bytes Data Write |
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