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W5100S Datasheet(PDF) 29 Page - WIZnet Co., Ltd |
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W5100S Datasheet(HTML) 29 Page - WIZnet Co., Ltd |
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29 / 110 page ![]() W5100S Datasheet Version1.2.5 29 / 110 3.1.17 UIPR (Unreachable IP Address Register) [RO] [0x002A-0x002D] [0x0000] When W5100S received Unreachable Packet (IR [UNR] = ‘1’), Peer IP Address in the Packet is written on UIPR. Ex) UIPR = “192.169.0.21” UIPR0(0x002A) UIPR1(0x002B) UIPR2(0x002C) UIPR3(0x002D) 192(0xC0) 168(0xA8) 0(0x00) 21(0x15) 3.1.18 UPORTR (Unreachable Port Register) [RO] [0x002E-0x002F] [0x0000] When W5100S received Unreachable Packet (IR [UNR] = ‘1’), Peer PORT Number in the Packet is written on UPORTR. Ex) UPORTR = 3000 (0x0BB8) UPORTR0(0x002E) UPORTR1(0x002F) 0x0B 0xB8 3.1.19 MR2 (Mode Register 2) [R=W] [0x0030] [0x40] MR2 configures System Operation Clock (SYS_CLK), Interrupt Activation, TCP & UDP Scan Prevention, WOL (Wake On LAN) and Force ARP. 7 6 5 4 3 2 1 0 CLKSEL IEN NOTCPRST UDPURB WOL - FARP - R=W R=W R=W R=W R=W W0 R=W W0 Bit Symbol Description 7 CLKSEL System Operation Clock(SYS_CLK) Select When CLKLCKR (Clock Lock Register) is Unlock, this bit can only set. (Ref 3.1.41 CLKLCKR (Clock Lock Register) [WO] [0x0070] [0x00]) 1 : 25MHz 0 : Depends on PHYCR1[PWDN] SYS_CLK selected by PHCR1 configuration. PHYCR1[PWDN] SYS_CLK 0 100 MHz |
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