W5100S datasheet(34/110 Pages) WIZNET

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W5100S Datasheet Version1.2.5

Write

0x01

Read

0x02

3.1.29 PHYDIVR (PHY Division Register)

[R=W] [0x0045] [0x01]

Internal Ethernet PHY uses the divided Clock of System Operation Clock (SYS_CLK). And this

divided Clock must not be exceeded 2.5MHz.

3.1.30 PHYCR0 (PHY Control Register 0)

[WO] [0x0046] [0x00]

PHYCR configures Ethernet PHY Operation Mode such as Auto Negotiation, Speed and Duplex.

Before set PHYCR, PHYLCKR (PHY Lock Register) must be on Unlock Mode.

MODE2

MODE1

MODE0

Bit

Symbol

Description

[7:3]

Reserved

[2:0]

MODE

MODE2 MODE1 MODE0

Description

Auto Negotiation

100BASE-TX FDX

100BASE-TX HDX

10BASE-TX FDX

10BASE-TX HDX

3.1.31 PHYCR1 (PHY Control Register 1)

[R=W] [0x0047] [0x41]

PHYCR1 configures Ethernet PHY Operation Mode such as PHY Power Down Mode, PHY Reset.

Before set PHYCR1, PHYLCKR (PHY Lock Register) must be on Unlock Mode.

WOL

PWDN

RST

Value

Divider

SYS_CLK=100MHz

SYS_CLK=25MH

0x00

1/32

3.125MHz (N/A)

781.25KHz

0x01

1/64

1.5625MHz

390.625KHz

others

1/128

781.25KHz

195.3125KHz

W5100S Datasheet(PDF) 34 Page - WIZnet Co., Ltd

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