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W5100S Datasheet(PDF) 27 Page - WIZnet Co., Ltd |
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W5100S Datasheet(HTML) 27 Page - WIZnet Co., Ltd |
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27 / 110 page  W5100S Datasheet Version1.2.5 27 / 110 S1 S0 S1 S0 S1 S0 S1 S0 Each SOCKET n RX Buffer Size is set by S0 and S1. Buffer Size S1 S0 1 KB 0 0 2 KB 0 1 4 KB 1 0 8 KB 1 1 3.1.12 TMSR (TX Memory Size Register) [R=W] [0x001B] [0x55] TMSR configures each SOCKET n TX Buffer Block Size. And the sum of SOCKET n TX Buffer Block Size must not be exceeded 8 Kbytes. (Ref Sn_TXBUF_SIZE (SOCKET n TX Buffer Size Register)) 7 6 5 4 3 2 1 0 SOCKET 3 SOCKET 2 SOCKET 1 SOCKET 0 S1 S0 S1 S0 S1 S0 S1 S0 Each SOCKET n TX Buffer Block Size is set by S0 and S1. Buffer Size S1 S0 1 KB 0 0 2 KB 0 1 4 KB 1 0 8 KB 1 1 3.1.13 IR2 (Interrupt Register 2) [RW] [0x0020] [0x00] When WOL Event occurs, IR2 [WOL] is set to ‘1’. If the Event occurs and IMR2 [WOL] is set to ‘1’ and internal Interrupt Pending Timer Counter is ‘0’, INTn is asserted to Low. When the Event is cleared or IMR2 [WOL] is set to ‘0’, INTn is de-asserted to High. 7 6 5 4 3 2 1 0 - - - - - - - WOL - - - - - - - WC |
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