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W5100S Datasheet(PDF) 14 Page - WIZnet Co., Ltd

Part # W5100S
Description  embedded Ethernet controller
PDF  110 Pages
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Manufacturer  WIZNET [WIZnet Co., Ltd]
Direct Link  https://www.wiznet.io/ko/Product/
Logo WIZNET - WIZnet Co., Ltd

W5100S Datasheet(HTML) 14 Page - WIZnet Co., Ltd

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W5100S Datasheet Version1.2.5
Low : Select
High : No Select
30
SCLK
ID
SPI Clock
On SPI Mode, it is used to SPI Clock.
But on Parallel Bus Mode, it must be connected to GND
or be floated.
31
1V2D
P
Digital 1.2V Power
Supplied from 1V20 voltage source.
32
MOSI
/ADDR0
IDM
SPI Master Output Slave Input / Address 0
MOSI : On SPI Mode, SPI Data is received from HOST
ADDR0 : On Parallel Bus Mode, it is used to Address 0
33
MISO
/ADDR1
IOPM
SPI Master Input Slave Output / Address 1
MISO : On SPI Mode, SPI Data is transmitted to HOST
ADDR1 : On Parallel Bus Mode, It is used to Address1
34
RDn
IU
Read Strobe
On Parallel Bus Mode, it indicates Read Operation
On SPI Mode, it must be connected to 3V3D or be floated
35
WRn
IU
Write Strobe
On Parallel Bus Mode, it indicates Write Operation.
36
3V3D
P
Digital 3.3V Power
37
DAT0
IOU
8 Bits Data Bus
On Parallel Bus Mode, DAT [7:0] receives Data from HOST
or W5100S.
On SPI Mode, DAT [7:0] must be floated.
38
DAT1
IOU
39
DAT2
IOU
40
DAT3
IOU
41
DAT4
IOU
42
DAT5
IOU
43
DAT6
IOU
44
DAT7
IOU
45
1V2D
P
Digital 1.2V Power
46
GND
P
Digital Ground
47
INTn
OP
Interrupt
When the event occurs during W5100S Ethernet
Communication, INTn notices to HOST.
Low : Interrupt Occurred
High : No Interrupt
(Ref IEN (Interrupt pin Enable) in MR2 (Mode Register 2),
INTPTMR (Interrupt Pending Time Register), IMR



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