W5100S datasheet(24/110 Pages) WIZNET

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W5100S Datasheet Version1.2.5

255 (0xFF)

3.1.4 SHAR (Source Hardware Address Register)

[R=W] [0x0009-0x000E] [0x00]

SHAR configures the Source MAC Address when NETLCKR (Network Lock Register) is on Unlock

Mode.

Ex) SHAR = “11:22:33:AA:BB:CC”

SHAR0(0x0009)

SHAR1(0x000A)

SHAR2(0x000B)

0x11

0x22

0x33

SHAR3(0x000C)

SHAR4(0x000D)

SHAR5(0x000E)

0xAA

0xBB

0xCC

3.1.5 SIPR (Source IP Address Register)

[R=W] [0x000F-0x0012] [0x00]

SIPR configures the Source IP Address when NETLCKR (Network Lock Register) is on Unlock Mode.

Ex) SIPR = “192.168.0.100”

SIPR0(x000F)

SIPR1(0x0010)

SIPR2(0x0011)

SIPR3(0x0012)

192 (0xC0)

168 (0xA8)

0 (0x00)

100(0x64)

3.1.6 INTPTMR (Interrupt Pending Time Register)

[R=W][0x0013-0x0014][0x0000]

INTPTMR sets internal Interrupt Pending Timer Count. When INTn is de-asserted to High, Timer

Count is initialized to INTPTMR and decreased by 1 from initial value to ‘0’ every SYS_CLK x 4.

When Interrupt occurs and the corresponding Interrupt Mask is set and INTPTMR is ‘0’, INTn is

asserted to Low.

Ex) INTPTMR = 1000(0x03EB)

INTPTMR0(0x0013) INTPTMR1(0x0014)

0x03

0xEB

3.1.7 IR (Interrupt Register)

[RW] [0x0015] [0x00]

When W5100S or SOCKET n Event occurs, the corresponding Bit in IR is set to ‘1’. If the Event

occurs and the corresponded Interrupt Mask Bit in IMR is set to ‘1’ and internal Interrupt Pending

Timer Counter is ‘0’, INTn is asserted to Low. When the Event is cleared or the corresponding

Mask Bit is set to ‘0’, INTn is de-asserted to High.

W5100S Datasheet(PDF) 24 Page - WIZnet Co., Ltd

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