TMS320F28375DPZP datasheet(104/226 Pages) TI

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8.10.1.2.2 ADC Characteristics (16-Bit Differential Mode)

over recommended operating conditions (unless otherwise noted)(6)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC conversion cycles(1)

29.6

31 ADCCLKs

Power-up time (after setting

ADCPWDNZ to first conversion)

500

µs

Gain error

–64

±9

LSBs

Offset error(2)

–16

±9

LSBs

Channel-to-channel gain error

±6

LSBs

Channel-to-channel offset error

±3

LSBs

ADC-to-ADC gain error

Identical VREFHI and VREFLO for all ADCs

±6

LSBs

ADC-to-ADC offset error

Identical VREFHI and VREFLO for all ADCs

±3

LSBs

DNL(3)

> –1

±0.5

LSBs

INL

–3

±1.5

LSBs

SNR(4) (11)

VREFHI = 2.5 V, fin = 10 kHz

87.6

THD(4) (11)

VREFHI = 2.5 V, fin = 10 kHz

–93.5

SFDR(4) (11)

VREFHI = 2.5 V, fin = 10 kHz

95.4

SINAD(4) (11)

VREFHI = 2.5 V, fin = 10 kHz

86.6

ENOB(4) (11)

VREFHI = 2.5 V, fin = 10 kHz,

single ADC(7)

14.1

bits

VREFHI = 2.5 V, fin = 10 kHz,

synchronous ADCs(8)

14.1

VREFHI = 2.5 V, fin = 10 kHz,

asynchronous ADCs(9)

Not

supported

PSRR

VDDA = 3.3-V DC + 200 mV

DC up to Sine at 1 kHz

PSRR

VDDA = 3.3-V DC + 200 mV

Sine at 800 kHz

CMRR

DC to 1 MHz

VREFHI input current

190

µA

ADC-to-ADC isolation(11) (5) (10)

VREFHI = 2.5 V, synchronous ADCs(8)

–2

LSBs

VREFHI = 2.5 V, asynchronous ADCs(9)

Not

supported

(1)

See Section 8.10.1.2.7.

(2)

Difference from conversion result 32768 when ADCINp = ADCINn = VREFCM.

(3)

No missing codes.

(4)

AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source

for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip

Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.

(5)

Maximum DC code deviation due to operation of multiple ADCs simultaneously.

(6)

Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterized with

VREFHI = 2.5 V and VREFLO = 0 V.

(7)

One ADC operating while all other ADCs are idle.

(8)

All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.

(9)

Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.

(10) Value based on characterization.

(11) I/O activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and

crosstalk.

TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

www.ti.com

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TMS320F28375DPZP Datasheet(PDF) 104 Page - Texas Instruments

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